Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling

In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach

Impact of negative and positive bias temperature stress on 6T-SRAM cells

With introduction of high-k gate oxide materials, the degradation effect <i>Positive Bias Temperature Instability</i> (PBTI) is starting to play an important role. Together with the still effective <i>Negative Bias Temperature Instability</i> (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event

Theory of circuit block switch-off

Switching-off unused circuit blocks is a promising approach to supress static leakage currents in ultra deep sub-micron CMOS digital systems. Basic performance parameters of Circuit Block Switch-Off (CBSO) schemes are defined and their dependence on basic circuit parameters is estimated. Therefore the design trade-off between strong leakage suppression in idle mode and adequate dynamic performance in active mode can be supported by simple analytic investigations. Additionally, a guideline for the estimation of the minimum time for which a block deactivation is useful is derived

A low-voltage BiCMOS power stage

A novel low-voltage class AB output stage integrated in BiCMOS technology is presented. It features a novel class AB low impedance output stage and has a simple but efficient quiescient current regulation. The amplifier exhibits a 3dB bandwidth of 5MHz while driving a combined parallel load of 30 /300pF at 2V power supply voltage. The voltage amplification of the output stage is greater than 1.0 which simplifies the design of the preceeding stage

Timing violations due to <i>V_DD/V_SS</i> bounce

The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed