Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub-45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (<i>g<sub>m</sub>/g<sub>DS</sub></i>) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies. To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks

LC-Oscillator featuring independent Gate biasing implemented in 32 nm CMOS technology

This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators

Assessment of the impact of technology scaling on the performance of LC-VCOs

This paper analyzes the scaling of LC voltage controlled oscillator (LC-VCO) implemented in advanced planar CMOS technologies. An LC-VCO for GSM applications, has been designed in state-of-the-art 45/40 nm and 32 nm CMOS technologies, exploiting different front- and back-end of line (FEOL/BEOL) options. The designs are compared with each other and with recent literature in terms of power and phase-noise performance

Reduction of Up-converted Flicker Noise in differential LC-VCO designed in 32nm CMOS technology

This paper deals with the design of LC Voltage Controlled Oscillator (LC-VCO) for GSM applications, implemented in a state-of-the-art 32 nm Planar CMOS technology. A standard VCO is compared with a topology featuring tail decoupling, which, to best of our knowledge, is used for the first time for a wide tuning-range application (i.e. 700 MHz centered at 3.65 GHz). The Decoupled VCO significantly reduces the Phase-Noise, up to 9 dB, by lowering the impact of the flicker noise introduced by the switching-pair on the 1/f3 region, with comparable current consumption and tuning-range with respect to the standard VCO

Design of UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET

This paper describes the design of a single-stage differential Low Noise Amplifier (LNA) for Ultra Wide Band(UWB) applications, implemented in state of the art Planar and FinFET 45nm CMOS technologies. A gm-boosted topology has been chosen and the LNA has been designed to work over the whole UWB band (3.1 \u2013 10.6GHz), while driving a capacitive load. The simulations highlight that, at the present stage of the technology development, the Planar version of the LNA outperforms the FinFET one thanks to the superior cutoff frequency fT of Planar devices in the inversion region, achieving comparable Noise Figure and voltage gain, but consuming less power

Design of UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET

This paper describes the design of a single-stage differential Low Noise Amplifier (LNA) for Ultra Wide Band(UWB) applications, implemented in state of the art Planar and FinFET 45nm CMOS technologies. A gm-boosted topology has been chosen and the LNA has been designed to work over the whole UWB band (3.1 \u2013 10.6GHz), while driving a capacitive load. The simulations highlight that, at the present stage of the technology development, the Planar version of the LNA outperforms the FinFET one thanks to the superior cutoff frequency fT of Planar devices in the inversion region, achieving comparable Noise Figure and voltage gain, but consuming less power

Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices

8This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To ensure a broadband input impedance matching, the g m-boosted topology has been chosen. Furthermore, the amplifiers have been designed to work over the whole UWB band (3.1-10.6 GHz), while driving a capacitive load, which is a realistic assumption for direct conversion receivers where the amplifier directly drives a mixer. The simulations (based on compact models obtained from preliminary measurements) highlight that, at the present stage of the technology development, the planar version of the circuit appears to outperform the FinFET one. The main reason is the superior cutoff frequency of planar devices in the inversion region, which allows the achievement of noise figure and voltage gain comparable to the FinFET counterpart, with a smaller power consumption.reservedmixedPONTON D; PALESTRI P; ESSENI D; SELMI L; TIEBOUT M; PARVAIS B; SIPRAK D; KNOBLINGER GPonton, Davide; Palestri, Pierpaolo; Esseni, David; Selmi, Luca; Tiebout, M; Parvais, B; Siprak, D; Knoblinger, G