The Chern character of {\theta}-summable Fredholm modules over dg algebras and localization on loop space

We introduce the notion of a {\vartheta}-summable Fredholm module over a locally convex dg algebra {\Omega} and construct its Chern character as a cocycle on the entire cyclic complex of {\Omega}, extending the construction of Jaffe, Lesniewski and Osterwalder to a differential graded setting. Using this Chern character, we prove an index theorem involving an abstract version of a Bismut-Chern character constructed by Getzler, Jones and Petrack in the context of loop spaces. Our theory leads to a rigorous construction of the path integral for N=1/2 supersymmetry which satisfies a Duistermaat-Heckman type localization formula on loop space

Post-contrast FLAIR imaging in a patient with posterior reversible encephalopathy syndrome (PRES).

We herein present a case of delayed enhancement of CSF on fluidattenuated inversion recovery (FLAIR) imaging in a patient with posterior reversible encephalopathy syndrome (PRES). In our case despite the settled clinical setting of PRES initial MR scan was negative and on repeated FLAIR imaging increased CSF signal intensity was more conspicuous than subtle cortical involvement

The First Thorough Side-Channel Hardware Trojan

Hardware Trojans have gained high attention in academia, industry and by government agencies. The effective detection mechanisms and countermeasures against such malicious designs are only possible when there is a deep understanding of how hardware Trojans can be built in practice. In this work, we present a mechanism which shows how easily a stealthy hardware Trojan can be inserted in a provably-secure side-channel analysis protected implementation. Once the Trojan is triggered, the malicious design exhibits exploitable side-channel leakage leading to successful key recovery attacks. Such a Trojan does not add or remove any logic (even a single gate) to the design which makes it very hard to detect. In ASIC platforms, it is indeed inserted by subtle manipulations at the sub-transistor level to modify the parameters of a few transistors. The same is applicable on FPGA applications by changing the routing of particular signals, leading to null resource utilization overhead. The underlying concept is based on a secure masked hardware implementation which does not exhibit any detectable leakage. However, by running the device at a particular clock frequency one of the requirements of the underlying masking scheme is not fulfilled anymore, i.e., the Trojan is triggered, and the device\u27s side-channel leakage can be exploited. Although as a case study we show an application of our designed Trojan on an FPGA-based threshold implementation of the PRESENT cipher, our methodology is a general approach and can be applied on any similar circuit

Agile acceleration of stateful hash-based signatures in hardware

With the development of large-scale quantum computers, the current landscape of asymmetric cryptographic algorithms will change dramatically. Today’s standards like RSA, DSA, and ElGamal will no longer provide sufficient security against quantum attackers and need to be replaced with novel algorithms. In the face of these developments, NIST has already started a standardization process for new Key Encapsulation Mechanisms (KEMs) and Digital Signatures (DSs). Moreover, NIST has recommended the two stateful Hash-Based Signatures (HBSs) schemes XMSS and LMS for use in devices with a long expected lifetime and limited capabilities for maintenance. Both schemes are also standardized by the IETF. In this work, we present the first agile hardware implementation that supports both LMS and XMSS. Our design can instantiate either LMS, XMSS, or both schemes using a simple configuration setting. Leveraging the vast similarities of the two schemes, the hardware utilization of the agile design increases by 20% in LUTs and only 3% in Flip Flops (FFs) over a standalone XMSS implementation. Furthermore, our approach can easily be configured with an arbitrary number of hash cores and accelerators for the one-time signatures for different application scenarios. We evaluate our implementation on the Xilinx Artix-7 FPGA platform, which is the recommended target for PQC implementations by NIST. We explore potential tradeoffs in the design space and compare our results to previous work in this field