Single component sleep-convention logic (SCL) modules

Describes a multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing VDD to both the first and second driver circuits. The first-rail logic circuit is coupled to VDD and ground, and has a first logic input and a first logic output. The second-rail logic circuit is coupled to VDD and ground, and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q1. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q0. The PMOS transistor has a gate driven by a SLEEP signal

Abstract An Analysis Methodology for Dynamic Power Gating

High leakage current in deep-submicrometer designs have become a significant contributor to total power dissipation of CMOS circuits, as short-channel transistors require lower power supply levels to reduce power consumption. This forces a reduction in the threshold voltage that causes a substantial increase of weak inversion current. As evidence of this effect, the 2006 Edition of the International Technology Roadmap for Semiconductors (ITRS) states that “Leakage will become a major industry crisis, threatening the survival of CMOS itself”. Among the leakage-control techniques that have been proposed so far, power gating, also known as MTCMOS, has traditionally been the most effective way to lower the leakage. This article describes a novel dynamic analysis methodology for power gated circuits which can be used as an electrical sign-off method for a full chip in deep sub-micrometer technology. The proposed methodology can achieve spice-comparable accuracy and full-chip-level performance for modern VLSI chip designs. 1