Analisi, simulazione e progettazione di un Theremin

Il Theremin, inventato nel 1919 dal fisico sovietico Leon Theremin, è uno dei primi strumenti musicali completamente elettronici. In questa tesi si discutono i principi fondamentali del funzionamento dello strumento, ed in seguito viene proposto un design completamente analogico che sfrutta però componenti elettronici moderni. Particolare attenzione è stata volta agli oscillatori in radiofrequenza, blocco fondamentale della generazione del suono prodotto dal Theremin

Gate leakage modeling in lateral β-Ga2O3 MOSFETs with Al2O3 gate dielectric

We present a detailed model of the static and dynamic gate leakage current in lateral β-Ga2O3 MOSFETs with an Al2O3 gate insulator, covering a wide temperature range. We demonstrate that (i) in the DC regime, current originates from Poole–Frenkel conduction (PFC) in forward bias at high-temperature, while (ii) at low temperature the conduction is dominated by Fowler–Nordheim tunneling. Furthermore, (iii) we modeled the gate current transient during a constant gate stress as effect of electron trapping in deep levels located in the oxide that inhibits the PF conduction mechanism. This hypothesis was supported by a TCAD model that accurately reproduces the experimental results

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit

Correlating Interface and Border Traps With Distinctive Features of C–V Curves in Vertical Al2_{\text{2}}O3_{\text{3}}/GaN MOS Capacitors

In this article, we present an analysis of the correlation between interface traps (ITs) and border traps (BTs) on distinctive features of C – V curves in vertical Al 2 O 3 /gallium-nitride (GaN) MOS capacitors. First, pulsed C – V curves were characterized during the application of quiescent gate bias stresses of different magnitudes and signs. This characterization revealed four main distinctive features: 1) rightward rigid shift; 2) leftward rigid shift; 3) decrease of the Δ C – Δ V slope; and 4) formation of a hump in a gate bias range before the accumulation of electrons at the oxide/semiconductor interface. By means of a combined experimental/simulation analysis, these features were univocally attributed to specific ITs or BTs in the overall trap distribution. The simulation-aided analysis enhances the physical understanding of the C – V curves features and increases the dependability of the adopted IT measurement technique, allowing for a more rapid process optimization and device technology development