Compact Real-Time Control System for Autonomous Vehicle

Due to global warming, there is an increase in the number of natural disasters occurring around the world. With more disasters happening, post disaster search and rescue personnel are putting their life on the line more often in scouting out the post disaster site and sending in first aid supplies while waiting for rescue vehicles like fire trucks and ambulance to arrive. In Malaysia alone, the use of compact autonomous landed vehicle (ALV) for this purpose is limited. There are many compact ALV that are being developed with microcontrollers and microprocessors such as Arduino and Raspberry Pi as the central control system, but they are fragile and can be damaged easily when used in harsh environments. In addition, multiple microcontrollers and microprocessors are needed for the ALV as parallel processing and limited gates are some of the common problems with microprocessors and microcontrollers. In this paper, a central control system using an FPGA is proposed together with the design of a prototype for the ALV. The ALV consists of three systems: Propulsion System, Sensor System, and Remote-Control System. These systems are integrated together with the Altera DE-115 board as the central control unit of the ALV. Verilog Hardware Description language (Verilog HDL) is used for designing the control system for the ALV. The proposed system is stable, low cost, allows parallel processing and the compact size of the ALV allows smooth manoeuvring through small areas of post disaster sites to scout out the area and send in first aid supplies to the victims

An Improved DC-DC Boost Converter for Energy Harvesting

A novel dual-input DC-DC boost converter that can perform the integration of harvested energy from solar and vibrational input energy sources is proposed. Firstly, the background of a hybrid energy system that relates to multi-input DC-DC converters is discussed, and the limitations of the current designs of power converter ICs are highlighted. A detailed design analysis of the proposed converter was done to justify its performance. A current and voltage stress analysis has been performed to ensure suitable switching devices are selected for the converter. Two different power control strategies are proposed for the DIDCB converter to manage output voltage during source and load-side disturbances. Performance analysis of the circuit is carried out using MATLAB Simulink software. Different duty ratios for power switches in the converter were tested to determine the maximum boost ratio and the highest efficiency that can be achieved by the converter. To demonstrate the feasibility of the proposed converter, the performance of the converter is compared with existing converter topologies. The proposed converter achieved a high efficiency of 99.4%, had less fluctuation in the output voltage, and had reduced overshoot. In addition, the proposed converter demonstrated a simpler configuration and required fewer component counts, which helped reduce the cost and size of the system

Novel Hybrid Metaheuristics And Algorithm Extensions For Optimization Of Engineering Applications

NP-hard optimization problems that are found in many engineering domains pose great challenges to traditional algorithmic solutions. The search space normally encompasses a huge number of local optimal and the computational effort to achieve a global optimum can be very huge for practical use. In this thesis, the design, analysis. improvement and application of metaheuristics for hard CO problems is presented. The research is motivated by four engineering applications that covers high-level synthesis, multiprocessor scheduling, flexible manufacturing systems and hybrid flow shop scheduling

Hardware Realization Of Fuzzy Wavelets Neural Network To Power Quality Analysis

This thesis presents a new approach aimed at automating the analysis of power quality disturbances. The approach focuses on the application of discrete wavelet transform technique to extract features from disturbance waveforms and their classification using a powerful combination of neural network and fuzzy logic. As there exists uncertainty in the training set and in the subsequent pattern recognition, fuzzy logic is used to determine the final output rather than taking the output of the neural network as the final classification, improving robustness in the system. The disturbances of interest include sag, swell, transient, fluctuation, interruption and normal waveform. Each power quality disturbance has unique deviations from the pure sinusoidal wave form and this is adopted to provide a reliable classification of disturbance

Hardware prototyping of Iris recognition system: A neural network approach

Iris recognition, a relatively new biometric technology, possesses great advantages, such as variability, stability and security, making it to be the most promising method for high security environments. A novel hardware-based iris recognition system is proposed in this paper, which consists of two main parts: image processing and recognition. Image processing involves histogram stress, thresholding, cropping, transformation and normalizing that is performed by using Matlab. Multilayer perceptron architecture with backpropagation algorithm is employed to recognize iris pattern. The entire architecture was modeled using VHDL, a hardware description language. The approach obtained a recognition accuracy of 98.5%. The design was successfully implemented, tested and validated on Altera Mercury EP1M120F484C5 FPGA utilizing 4157 logic cells and achieved a maximum frequency of 121.87 MHz. This novel and efficient method in hardware, based on FPGA technology showed improved performance over existing approaches for iris recognitio

VHDL modelling of the open short tester

IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test

Adaptive GA: An Essential Ingredient in High-Level Synthesis

High-level synthesis, a crucial step in VLSI and System on Chip (SoC) design, is the process of transforming an algorithmic or behavioral description into a structural specification of the architecture realizing the behavior. In the past, researchers have attempted to apply GAs to the HLS domain. This is motivated by the fact that the search space for HLS is large and GAs are known to work well on such problems. However, the process of GA is controlled by several parameters, e.g. crossover rate and mutation rate that largely determine the success and efficiency of GA in solving a specific problem. Unfortunately, these parameters interact with each other in a complicated way and determining which parameter set is best to use for a specific problem can be a complex task requiring much trial and error. This inherent drawback is overcome in this paper where it presents two adaptive GA approaches to HLS, the adaptive GA operator probability (AGAOP) and adaptive operator selection (AOS) and compares the performance to the standard GA (SGA) on eight digital logic benchmarks with varying complexity. The AGAOP and AOS are shown to be far more robust than the SGA, providing fast and reliable convergence across a broad range of parameter settings. The results show considerable promise for adaptive approaches to HLS domain and opens up a path for future work in this area

Power optimization in hybrid Visible Light Communication for indoor applications

High efficiency LEDs are widely used to replace fluorescent lamps due to outstanding energy efficiency, long operational life and affordable manufacturing cost. LED contains dual fundamental applications, which are lighting illumination and Visible Light Communication (VLC). Although VLC provides several advantages when compared with RF wireless communication, duplex communication of VLC can be problematic. Hybrid visible light communication (HVLC) is proposed to solve the limitation of VLC and fulfil mobile internet requirement which integrates VLC for downlink and Wi-Fi for uplink. Visual effect based on interior design criteria is taken into account when users replace fluorescent lamp with LED. Thus, the project investigates the optimal condition between the lighting requirement and data connectivity. Two case studies are chosen to demonstrate our proposed optimization scheme namely school hall design (square topology) and hotel design (ring topology). A linear optimization scheme is proposed for received power among the mobile users in school hall (square topology) and hotel lobby (ring topology). This technique is addressed for a practical room scenario of dimension 30m × 30m × 3m where 90 users are randomly generated with different positions. Light sources placement also affected the performance of VLC. Based on our simulation, square topology have higher signal-to-noise ratio (SNR) if compared to ring topology

Expert System for Power Quality Disturbance Classifier

Identification and classification of voltage and current disturbances in power systems are important tasks in the monitoring and protection of power system. Most power quality disturbances are non-stationary and transitory and the detection and classification have proved to be very demanding. The concept of discrete wavelet transform for feature extraction of power disturbance signal combined with artificial neural network and fuzzy logic incorporated as a powerful tool for detecting and classifying power quality problems. This paper employes a different type of univariate randomly optimized neural network combined with discrete wavelet transform and fuzzy logic to have a better power quality disturbance classification accuracy. The disturbances of interest include sag, swell, transient, fluctuation, and interruption. The system is modeled using VHSIC Hardware Description Language (VHDL), a hardware description language, followed by extensive testing and simulation to verify the functionality of the system that allows efficient hardware implementation of the same. This proposed method classifies, and achieves 98.19% classification accuracy for the application of this system on software-generated signals and utility sampled disturbance events