3D GaN nanoarchitecture for field-effect transistors

The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1-100) and diameters (i.e., 220-640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics

Top-Down Fabrication of Arrays of Vertical GaN Nanorods with Freestanding Top Contacts for Environmental Exposure

Arrays of 1D-vertically arranged gallium nitride (GaN) nanorods (NRs) are fabricated on sapphire and connected to both bottom and freestanding top contacts. This shows a fully validated top-down method to obtain ordered arrays of high-surface-to-volume elements that can be electrically interrogated and used, e.g., for sensing applications. Specifically, these will be used as highly integrated heating elements for conductometric gas sensors in self-heating operation. Detailed fabrication and processing steps involving inductively coupled plasma reactive ion etching (ICP-RIE), KOH-etching, interspace filling, and electron-beam physical vapor deposition technologies are discussed, in which they can be well adjusted and combined to obtain vertical GaN NRs as thin as 300 nm in arbitrarily large and regular arrays (e.g., 1 × 1, 3 × 3, 9 × 10 elements). These developed devices are proposed as a novel sensor platform for temperature-activated measurements that can be produced at a large scale offering low-power, and very stable temperature control

Vertical 3D GaN Nanoarchitectures towards an Integrated Optoelectronic Biosensing Platform in Microbial Fuel Cells

An integrated nano-optoelectronic biological sensor system is developed to obtain insights of the biochemical and physical processes of Geobacter sulfurreducens-based biofilm growth inside a miniaturized microbial fuel cell (MFC) reactor. Gallium nitride (GaN), which was used as a novel electrode material, has been investigated in terms of its biocompatibility and performance to transport the electrons delivered by the microorganisms. Moreover, in order to enhance the produced current density, vertical 3D GaN nanoarchitectures (i.e., arrays of nanowires and nanofins) with larger surface-to-volume ratios were fabricated using a top-down nanomachining method involving nanolithography and hybrid etching technique

Nanofabrication of Vertically Aligned 3D GaN Nanowire Arrays with Sub-50 nm Feature Sizes Using Nanosphere Lift-off Lithography

Vertically aligned 3D gallium nitride (GaN) nanowire arrays with sub-50 nm feature sizes were fabricated using a nanosphere lift-off lithography (NSLL) technique combined with hybrid top-down etching steps (i.e., inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching). Owing to the well-controlled chemical surface treatment prior to the nanobead deposition and etching process, vertical GaN nanowire arrays with diameter of ~35 nm, pitch of ~350 nm, and aspect ratio of >10 could be realized using 500 nm polystyrene nanobead (PN) masks. This work has demonstrated a feasibility of using NSLL as an alternative for other sophisticated but expensive nanolithography methods to manufacture low-cost but highly ordered 3D GaN nanostructures