Ultra-Fast All-Optical Half Subtractor Based on Photonic Crystal Ring Resonators

Abstract: In this paper, we aim to design and propose a novel structure for all-opticalhalf subtractor based on the photonic crystal. The structure includes two optical switches,one power splitter, and one power combiner. The optical switches are made of theresonant rings which use the nonlinear rods for dropping operation. The footprint of thedesigned structure is about 602 μm2 that is more compact than one in most works.Furthermore, despite some works, the input signals are the same in the phase angle andthe optical power. Also, each input signal is applied to one port while this issue has notbeen considered in some works. Plane wave expansion and finite difference time domainmethods are used to calculate the band diagram and simulation of the optical wavepropagation throughout the structure, respectively. The maximum obtained rise time ofall states of the proposed device is just about 1.4 ps. Besides, the presented structure iscapable of working at the third communication window so it can be matched with opticalfiber transmission systems

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

Time to digital converter (TDC) is a key block for time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented. The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited. The proposed converter features high accuracy, very small average error and high linear range. Also this converter has some advantages such as low circuit complexity, low power consumption and low sensitive to the temperature, power supply and process changes (PVT) compared with the time to digital converters that used preceding conversion techniques. The proposed converter uses an indirect time to digital conversion method. Therefore, our converter has the appropriate linearity without extra elements. In order to evaluate the proposed idea, an integrating time to digital converter is designed in 0.18 μm CMOS technology and was simulated by Hspice. Comparison of the theoretical and simulation results confirms the proposed TDC operation; therefore, the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals

Analysis and Design of a New Voltage Amplifier Applying In The Time and Voltage Domain Converters

In this paper a new voltage amplifier is investigated which is employed in the time and voltage domain converters such as analog to digital converters (ADCs) and time to digital converters (TDCs). The time and voltage amplifiers are used in the time and voltage domain converters for increasing the time resolution and accuracy. The voltage and time amplifiers are basically utilized in the ADCs and TDCs which employ the pipeline or interpolation techniques for digitizing the time interval between two input signals. In these converters, the main time or voltage residue is ampliï‌ed by a time or voltage amplifier and fed to the next stage. The proposed voltage amplifier uses a charge pump technique for voltage amplification. The proposed circuit does not use delay lines in its structure and features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variation and high accuracy compared with the time or voltage amplifiers which previously proposed. The amplifier improves dynamic range of the converters. Therefore, the amplifier produces a exact voltage gain. Also, the linear range of the proposed voltage amplifier is appropriate

A high precision logarithmic-curvature compensated all CMOS voltage reference

This paper presents a resistor-less high-precision, sub-1 V all-CMOS voltage reference. A curvature-compensation method is used to cancel the logarithmic temperature dependence regardless of mobility temperature exponent (γ). The circuit is simulated in 65 nm CMOS technology and yields an output voltage of 594 mV, temperature coefficient of 7ppm∘C in the range of −40 to 125 °C, a power supply rejection ratio (PSRR) of − 43 dB at of 100 Hz, a line sensitivity of 76μVV in the supply voltage range of 1.2 to 2 V, a power dissipation of 1.4μW at 1.2 V supply and an output noise of 2.8μVHz at 100Hz. The total active area of the design is 0.03mm2. This voltage reference is suitable for low-power, low-voltage applications which also require high precision

An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent (γ). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 ppm∘C in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of 6μVV in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 μV/Hz at 100 Hz. The total active area of the design is 0.03 mm2. This voltage reference is suitable for low-power low-voltage applications which also require high precision