Bus energy consumption for multilevel signals

A comprehensive analysis of energy consumption for voltage-mode multilevel signals on a nanometer-technology bus is presented. A transition-dependent model is used which allows simplified calculation of the energy consumption. The accuracy of the approach is demonstrated using circuit simulations of three different electrical models of the bus, namely, lumped-C, distributed-RC, and distributed-RLC networks. We also verify that bus energy consumption is independent of driver resistance, as predicted by the model. Finally, we present a comparative analysis of power consumption for multilevel and binary buses

Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication

The AWGN channel is characterized and verified for 4-PAM signaling. Based on that, three fault tolerant on/off-chip communication architectures using block codes alongside 4-PAM modulation have been evaluated. The results display decent improvement in BER performance while keeping complexity as low as possible

A framework for system dependability validation under the influence of intrinsic parameters fluctuation

This paper presents a framework to analyze and evaluate effects of cell failures induced by impact of intrinsic parameters fluctuation (IPF) on system dependability. The method of evaluation is based on generating the actual cell failures model and the realistic conditions of hardware-software interactions, where the actual error pattern can be captured. The case study of this paper is the impact of cell failures in L1 data cache of a general-purpose microprocessor. The failure modules are generated corresponding to the individual and combined impact of IPF sources in nanometer scale Ultra Thin Body – Silicon on Isolator (UTB-SOI) transistor on 6T-SRAM cell stability. A novel fault injection mechanism has been introduced to propagate errors, through modifying data of cache transactions according to error(s) incurred, dynamically at system-level. By applying a representative system workload using a well-selected suit of real benchmark programs, this study demonstrates that the framework: 1) provides an accurate user visible description for the implications of cell failures at the higher levels of abstraction induced by IPF sources at the lower levels of abstraction, 2) links individual and combined impact of IPF sources with the corresponding implications at system-level which offers a tool to systems designer to involve IPF impacts within the design plan, 3) allows for a detailed simulation process of a system-level environment in the presence of cell failures induced by IPF within an accepted period of time using the look-up file technique and thus offers a foundation to system dependability studies that require vast statistical models, 4) offers high credible evaluation results because the framework is based on the actual error pattern incurred in the system, and 5) improves system reliability where it offers valuable perceptions for an optimal fault tolerance technique in L1 cache with a high failures rate

Development and evaluation of an impedance spectroscopy sensor to assess cooking oil quality

When the cooking oil is used repeatedly, several unwanted substances are generated, which may cause health problems. This study was conducted to determine the possibility of using the impedance spectroscopy to differentiate among varying cooking oil quality at various intervals of heating time at constant temperature. The frequency has started from 100 Hz to 100kHz. Fresh, 10-hour, 20-hour, 30-hour, and 40-hour heated cooking oil was prepared by using lab oven at temperature of 180oC. In this study, a sensing probe was designed to measure the electrical properties of the oil samples. The oil samples were analyzed using a viscometer to measure the viscosity of the oil, a sensor to measure total polar compound (TPC), and an impedance probe connected to a LCR meter to measure the electrical properties of the oil. The measurements were analyzed and correlated with oil quality parameters obtained from a viscometer and a sensor of TPC. The discrimination between different heated hours of oil samples was examined and the results were compared to their physico-chemical properties such as viscosity and total polar compounds. The effect of heating of frying oils were successfully evaluated and discriminated using the impedance spectroscopy. Significant correlations (r -0.98472) were found between changes in total polar compound properties of oil and the impedance values

Impact of intrinsic parameter fluctuation on the fault tolerance of L1 data cache

As the semiconductor process technology continues to scale deeper into the nanometer region, the intrinsic parameter fluctuations will aggressively affect the performance and reliability of future microprocessors and System-on-Chip (SoC) applications. These system requires large SRAM arrays that occupy an increasing fraction of the chip real estate. To investigate the impact various source of intrinsic parameter fluctuation (IPF) from systems point of view, a framework to bridge architecture-level and device-level simulation will be utilized for data cache built from transistors with 25 nm, 18 nm and 13 nm technology node. This study found that the IPF will not have any significant impacts on data cache memory systems build with 25 nm while increasing the memory cell ratio, (ß) to two will overcome the IPF impacts for the 18 nm. However, the 13 nm technology data cache could not operate even with higher cell ratio. Common, cache memory fault detection and correction such as ECC and redundancy can only partially remove the transaction error caused by these fluctuation sources

Wireless sensor network for structural health monitoring: a contemporary review of technologies, challenges, and future direction

The importance of wireless sensor networks in structural health monitoring is unceasingly growing, because of the increasing demand for both safety and security in the cities. The speedy growth of wireless technologies has considerably developed the progress of structural monitoring systems with the combination of wireless sensor network technology. Wireless sensor network–based structural health monitoring system introduces a novel technology with compelling advantages in comparison to traditional wired system, which has the benefits of reducing installation and maintenance costs of structural health monitoring systems. However, structural health monitoring has brought an additional complex challenges in network design to wireless sensor networks. This article presents a contemporary review of collective experience the researchers have gained from the application of wireless sensor networks for structural health monitoring. Technologies of wired and wireless sensor systems are investigated along with wireless sensor node architecture, functionality, communication technologies, and its popular operating systems. Then, comprehensive summaries for the state-of-the-art academic and commercial wireless platform technologies used in laboratory testbeds and field test deployments for structural health monitoring applications are reviewed and tabulated. Following that, classification taxonomy of the key challenges associated with wireless sensor networks for structural health monitoring to assist the researchers in understanding the obstacles and the suitability of implementing wireless technology for structural health monitoring applications are deeply discussed with available research efforts in order to overcome these challenges. Finally, open research issues in wireless sensor networks for structural health monitoring are explored

Optimality of bus-invert coding

Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an M-bit bus into P subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a 2P-state trellis

VLSI implementation of huffman design using FPGA with a comprehensive analysis of power restrictions

Lossless compression is important in Information hypothesis as well as today's IT field. Lossless design of Huffman is most to a large degree used in the compression arena. However, Huffman coding has some limitations where it depends on the stream of symbols appearing in a file. In fact, Huffman coding creates a code with very few bits for a symbol that has a very high probability of occurrence and an utmost number of bits for a symbol with a low probability of occurrence. In this work Hardware implementation of static Huffman coding for data compression using has been designed, this hardware contains both encoder and decoder-based hardware. The proposed systems Altera DE-2 Board have been used in order to implement the text data compression. The experiments with a simulated environment and the real-time implementation for FPGA with Synopsys power analysis show that constraint has been fulfilled and the target design of the buffer length is appropriate. Power consumption that achieved by the proposed algorithm was 0.0161 mW with frequency 20MHz.and 0.1426 mW with frequency 180MHz within the design limitations. The proposed design is implemented by using ASIC and FPGA design methodologies. In order to implement the encoder and decoder architectures, 130 nm standard cell libraries was used for ASIC implementation. The simulations are carried out by using Modelsim tool. The architecture of compression and decompression algorithm design has been created using Verilog HDL language. Quartus II 11.1 Web Edition (32-Bit). In addition, simulated using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition. And it is implemented using Altera FPGA (DE2) for real time implementation

Runtime CPU scheduler customization framework for a flexible mobile operating system

Mobile operating systems should adapt to different applications requirement such as multimedia, games, video and audio applications, and mobile calls, etc. Process scheduling is considered as the most important part of the mobile operating system, which has the responsibility for adapting the operating systems to these applications requirements. In this work, the architecture for a runtime CPU scheduler customization framework for the Linux kernel that take into account different applications requirements is presented. The Runtime CPU Scheduler Customization (RCSC) framework permits the mobile devices users as well as the developers of Linux-based mobile operating systems to customize CPU scheduler to run with a specific scheduling policy as well as evaluate newly developed scheduling policies from user space at runtime. As a consequence, mobile operating system can be tuned manually or automatically in order to adapt with the requirements of a particular application

A low quiescent current low dropout voltage regulator with self-compensation

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is self-attained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology