Silicon Nanowire Based Photodetectors: Modeling and Fabrication

This research is focused on investigating the role of silicon nanowires in designing high gain, high sensitivity photodetectors, and is based on both device modeling and fabrication. We demonstrate that the superior electrostatic control within the nanowires enables us to effectively engineer the energy band and design novel photodetector architectures. This is due to the high surface to volume ratio in nanowires which allows for the ability to change the electrical properties of a nanowire device in response to a voltage applied to the gate contact. In the first part of the thesis, two photodetector geometries are proposed and theoretically studied. The first geometry is a Metal Oxide Semiconductor (MOS) device with nanowires incorporated in its channel. The next geometry is a junction-less phototransistor, e.g. a photoconductor with a third terminal as the gate. Both geometries are important due to their ability to generate optical gain. For both cases, first the role of nanowire parameters and their pros and cons on the device photo-response is investigated. Afterwards, we propose modifications to the device geometry in order to improve the performance of the device in terms of optical gain and sensitivity. The first modification is allocating a wide region for light absorption in the channel, since single nanowire based photodetectors suffer from lack of efficient absorption, due to their small cross sectional area. Use of phototransistors also helps the photo-current increase, due to the device's internal gain. The second modification incorporates two nanowire/ gate geometries to improve the device photo-response, in terms of both dark- and photo-current. The charge flow in each nanowire is controlled by a gate, which changes the energy band within the nanowire. This band engineering allows for both increasing the optical gain of the phototransistor, and keeping the dark current low. We report nanowire based phototransistors that are potentially able to detect low levels of light intensity (photon rate of less than 50/s). The second part of the thesis is devoted to the fabrication of the nanowire based structures. Top-down approach is used, mainly due to the better control on the nanowire size and position, and repeatability of the processes involved. Fabrication process includes several steps of electron beam lithography, dry and wet etching, metal and dielectric deposition and annealing. Pre-developed recipes are used when available. New recipes are also developed to better suit the specific needs of the devices. The measurement results of the fabricated structures verify most of the concepts proposed in the modeling phase. In the third part of this thesis, we characterize MOS capacitors with and without illumination, based on Silicon on Insulator (SOI) structures used in the previous chapters. Here, we report the first observation of photon induced negative capacitance in a conventional Metal Oxide Semiconductor (MOS) capacitor without the use of ferroelectric materials. Design and implementation of this phenomenon is presented in a capacitor where an aluminum oxide layer serves as the gate dielectric, and the capacitor is in depletion mode. Through extensive modeling, we establish that trap states at the semiconductor-oxide interface, coupled with the injection of photo-generated electrons are responsible for the negative capacitance. We find that varying the trap density and/or light intensity can tune the value of the negative capacitance. We show that in the presence of photons, the experimentally measured quasi-static capacitance in depletion is almost twice the value without photons. Further, the measured capacitance is larger than the values in accumulation and inversion.1 yea

Phononic loss in superconducting resonators on piezoelectric substrates

We numerically and experimentally investigate the phononic loss for superconducting resonators fabricated on a piezoelectric substrate. With the help of finite element method simulations, we calculate the energy loss due to electromechanical conversion into bulk and surface acoustic waves. This sets an upper limit for the resonator internal quality factor $Q_i$. To validate the simulation, we fabricate quarter wavelength coplanar waveguide resonators on GaAs and measure $Q_i$ as function of frequency, power and temperature. We observe a linear increase of $Q_i$ with frequency, as predicted by the simulations for a constant electromechanical coupling. Additionally, $Q_i$ shows a weak power dependence and a negligible temperature dependence around 10$\,$mK, excluding two level systems and non-equilibrium quasiparticles as the main source of losses at that temperature

Modeling and Harmonic Balance Analysis of Parametric Amplifiers for Qubit Read-out

Predicting the performance of traveling-wave parametric amplifiers (TWPAs) based on nonlinear elements like superconducting Josephson junctions (JJs) is vital for qubit read-out in quantum computers. The purpose of this article is twofold: (a) to demonstrate how nonlinear inductors based on combinations of JJs can be modeled in commercial circuit simulators, and (b) to show how the harmonic balance (HB) is used in the reliable prediction of the amplifier performance e.g., gain and pump harmonic power conversion. Experimental characterization of two types of TWPA architectures is compared with simulations to showcase the reliability of the HB method. We disseminate the modeling know-how and techniques to new designers of parametric amplifiers.Comment: 13 pages, 15 figure

Mitigation of frequency collisions in superconducting quantum processors

The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal crosstalk imposes constraints on the frequency separation between neighboring qubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e. 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only 3 collisions between quantum-gate transition frequencies, assuming 2% crosstalk and 99.9% target gate fidelity.Comment: 8 figures, 18 pages (8 pages main text), units fixed in Fig. 1

Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits

We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q > 1.5 7 1 0 6). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5 7 0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%-2.5%. We show that 60%-70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer

Three-wave mixing traveling-wave parametric amplifier with periodic variation of the circuit parameters

We report on the implementation of a near-quantum-limited, traveling-wave parametric amplifier that uses three-wave mixing (3WM). To favor amplification by 3WM, we use superconducting nonlinear asymmetric inductive element (SNAIL) loops, biased with a dc magnetic flux. In addition, we equip the device with dispersion engineering features to create a stopband at the second harmonic of the pump and suppress the propagation of the higher harmonics that otherwise degrade the amplification. With a chain of 440 SNAILs, the amplifier provides up to 20 dB gain and a 3-dB bandwidth of 1 GHz. The added noise by the amplifier is found to be less than one photon

Three-wave mixing traveling-wave parametric amplifier with periodic variation of the circuit parameters

We report the implementation of a near-quantum-limited, traveling-wave parametric amplifier that uses three-wave mixing (3WM). To favor amplification by 3WM, we use the superconducting nonlinear asymmetric inductive element (SNAIL) loops, biased with a dc magnetic flux. In addition, we equip the device with dispersion engineering features to create a stop-band at the second harmonic of the pump and suppress the propagation of the higher harmonics that otherwise degrade the amplification. With a chain of 440 SNAILs, the amplifier provides up to 20 dB gain and a 3-dB bandwidth of 1 GHz. The added noise by the amplifier is found to be less than one photon.Comment: 6 pages, 6 figure