Face detection using classifiers cascade based on vector angle measure and multi-modal representation

This paper deals with face detection in still gray level images which is the first step in many automatic systems like video surveillance, face recognition, and images data base management. We propose a new face detection method using a classifiers cascade, each of which is based on a vector angle similarity measure between the investigated window and the face and nonface representatives (centroids). The latter are obtained using a clustering algorithm based on the same measure within the current training data sets, namely the low confidence classified samples at the previous stage of the cascade. First experiment results on refereed face data test sets are very satisfactory

Lower-power TSPC-based domino logic circuit design with 2/3 clock load

In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit design. Compared to using three clock transistors in the conventional TSPC-based scheme, the proposed circuit only requires two transistors. As a result, the clock load capacitance is reduced, leading to low power consumption in the clock distribution network. A keeper design to solve charge sharing is also demonstrated. Simulation results using 90nm and 45nm CMOS technologies are provided and discussed, respectively, which illustrate power saving as compared to conventional design not only when the input logic is active but also when the input logic is held to zero. © 2011 Published by Elsevier Ltd

An 84 pW/frame per pixel current-mode CMOS image sensor with energy harvesting capability

In this paper, we present an ultra-low-power current-mode image sensor with energy harvesting capability. By biasing the in-pixel transconductance amplifier in triode region and using a pipelined 9-bit current-mode analog-to-digital converter (ADC), a power consumption as low as 84 pW/frame per pixel is achieved. Besides the ultra-low-power feature, the proposed 6T pixel can also be used as a solar cell by reconfiguring the in-pixel P +Nwell photodiode, which can generate several micro watt power at Klux illumination levels. As a result, this energy harvesting imager is very suitable for wireless image sensor network applications. The test chip with a 128 × 96 pixel array resolution is fabricated using a 0.35 μ m CMOS technology. The random noise and the fixed pattern noise (FPN) in dark are 0.4% and 1%, respectively. In the energy harvesting mode, 4.85 μW power can be harvested using the reconfigurable pixel array. © 2011 IEEE

A current mode CMOS imager using shunting inhibition-based dynamic range compression

An ultra-wide dynamic range current-mode CMOS imager is presented. It achieves dynamic range compression by using biologically inspired shunting inhibition vision models. As a result, it features retina-like characteristics, enabling the sensor to adapt to a wide range of scene illumination conditions. Local image contrast and edge information are preserved and can be further enhanced. The properties of the shunting inhibition-based dynamic range compression can be defined by a simple set of externally-tunable parameters, making the proposed current-mode CMOS imager architecture fully programmable. The prototype was designed in full custom ALCATEL 0.5μm CMOS technology

A scalable low power imager architecture for compound-eye vision sensors

In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using Address-Event-Representation (AER). The proposed AER approach to compound-eye Imaging enables low power operation (lOnA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and Increased noise levels. © 2005 IEEE

A novel scalable spiking pixel architecture for deep submicron CMOS technologies

In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes. © 2006 IEEE

Dynamic voltage and frequency scaling for low-power multi-precision reconfigurable multiplier

In this paper, a 32x32-bit low power multi-precision multiplier is described, in which each building block can be either an independent smaller-precision multiplier or work in parallel to perform higher-precision operations. The proposed multi-precision multiplier enables voltage and frequency scaling for low power operation, while still maintaining full throughput. According to user's arbitrary throughput requirements, the highly dynamic voltage and frequency scaling circuits can autonomously configure the multiplier to operate with the lowest possible voltage and frequency to achieve the lowest power consumption. By carrying out optimizations at the algorithmic and architectural levels, we have completely removed silicon area and power overheads which is always associated with the reconfigurability features. The 32x32-bit low power multiprecision multiplier has been implemented in TSMC 0.18 μm technology. Compared with fixed-width multipliers, the proposed design features around 13.8% and 30% reduction in circuit area and power, respectively. Multi-precision processing featured in this paper accordingly enables voltage and frequency scaling resulting in up to 68% reduction in power consumption. ©2010 IEEE

An ultra-low power operating technique for mega-pixels current-mediated CMOS imagers

A novel ultra-low power operating technique is presented for Mega-pixels current-mediated CMOS imagers. In the proposed technique, the reset and read-out phases occur simultaneously. as a single pixel is being read-out another pixel is being reset. Such a strategy reduces power consumption by more than 2 orders of magnitude for current-mediated Mega-pixels CMOS imagers, while still allowing for on-read-out, fixed pattern noise correction. Power consumption becomes independent of both read-out speed and imager array size. Additionally, the proposed operating technique leads to improved linearity for the pixel response, increased dynamic range as well as on-chip digital shutter functionality. A single additional address decoder is required to generate the reset signals, resulting in a marginal increase in silicon area. The wiring overhead is kept to a minimum with only a single control signal required to operate the current- mediated CMOS imager(1)

A novel ultra-low power reset/read-out technique for megapixels current-mode CMOS imagers

A novel reset/read-out technique is presented for current-mode ultra-low power Megapixels CMOS imagers. In the proposed technique, the reset and readout phases occur simultaneously: as a single pixel is being read-out another pixel is being reset. Such a strategy is shown to result in a significant reduction in power consumption. Furthermore, power consumption becomes independent of both read-out speed and imager array size, while still allowing for on read-out FPN correction along with external electronic shutter control. Its potential integration into CMOS imagers, is demonstrated through the full custom design of a programmable 32x32 current-mode CMOS imager in AMIS CMOS 0.35mum technology