Portrait of Morris Lurie taken during an oral history interview,1 March 1978 [picture] /

Title from acquisitions documentation.; Part of the: Hazel de Berg collection of photographs.; Morris Lurie interviewed by Hazel de Berg in the Hazel de Berg collection; Located at; National Library of Australia Oral History collection ORAL TRC 1/1081

A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits

A method for maximum power estimation in CMOS VLSI circuits is proposed. The method is based on extreme value theory and allows for the calculation of the upper end point of the probability distribution which is followed by the instantaneous power drawn from the supply bus. The main features of the method are the relatively small and circuitin-dependent subset of input patterns required for accurate prediction of maximum power and its simulative nature which ensures that no over-simplifying assumptions are made. Application of the proposed method to eight distributions, which come close to the behavior of power consumption in VLSI circuits, proved its superior capabilities with respect to existing methods

A statistically-based engine for P/G network optimization

The problem of optimum design of general (tree or graph-based) power distribution networks with respect to the voltage drop effect is addressed in this paper. A rigorous formulation based on linear circuit theory is established for the relevant constrained optimization problem, so that the resultant network occupies the minimum possible area under specific voltage drop constraints at all IC functional blocks. The necessary maximum current estimates for the optimization procedure are accurately obtained - by statistical means - from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit

Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuit's major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit. ©2004 IEEE

A design flow for the precise identification of the worst-case voltage drop in power grid analyses

Modern IC designs contain hundreds of millions of transistors and new implementations of multi core chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow based on innovative results from recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine within an industrial EDA flow for performing power grid verification using a custom hierarchical design. © 2008 IEEE

An RTL-to-grid design flow for power grid verification based on a statistical estimation engine

The most important reliability problem of modern power distribution networks is the voltage drop or IR-drop problem. In this paper we present a design flow based on industrial tools for power grid verification, where the grid is modeled as a linear resistive network and the necessary maximum current estimates are statistically obtained by recent advances in the field of extreme value theory. Experimental results include the verification of power grid for a choice of different real designs. © 2006 IEEE

A power grid analysis and verification tool based on a statistical prediction engine

Voltage drops are one of the most stringent problems in modern IC implementation, which is exacerbated by the ever decreasing transistor sizes and interconnect line widths. In order to find the true worst case voltage drop that a power net of a design might suffer, the designer would have to check the voltage drops that occur from the simulation of all possible input vector pairs of a design. This is a prohibitive amount of simulations for modem ICs that have hundreds of inputs. Consequently, designers face two basic challenges, fast and accurate estimation of worst case voltage-drop and accurate modeling of the power distribution network. In this paper we present a voltage-drop aware tool for power grid analysis and verification based on a statistical engine, which can estimate the true worst case voltage drops on a design with a typical confidence level of 99%. The statistical engine is based on extensions to the Extreme Value Theory (EVT) which is a pertinent field of statistics for the estimation of the unknown maximum of a related population from one (or more) of its samples. The paper shows how the statistical engine can take input from gate-level simulation of digital logic, combined with transient simulation of the power and ground network with inductance-aware (RLCK) models. Using these techniques, a designer can estimate the true worst case voltage drop on each and every contact of the power and ground distribution network of a digital design, using a relatively small amount of input vectors, thus greatly reducing the turnaround time for power integrity verification. ©2010 IEEE