Third Order Distortion Measurement Circuit for CMOS Transconductors

Linear transconductor circuits with an electronically variable transconductance are frequently used as building blocks for linear signal processing, especially at high frequencies (e.g. in Transconductor-C filters and AGC amplifiers). The distortion of these circuits is one of the main issues that limits the dynamic range. In principle, distortion compensation techniques can be conceived [1], [2]. However, the design of circuits with reliable distortion compensation is hindered by two causes: First, the models for nonlinear behaviour are not accurate enough [1], [2]. Second, the nonlinearity may vary with IC-processing, temperature and ageing. An integrated distortion measurement and control circuit could be a crucial step in the solution of these problems. To examine the feasibility of this concept, a design project aiming at an integrated third order derivative measurement circuit in full CMOS has been pursued. Simulation results indicate that a HD 3 resolution of 0.1 % can be achiev..

A 100&#x2013;800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <formula formulatype="inline"><tex Notation="TeX"><-</tex></formula>40 dBc for ALL Harmonics

Radio transceivers capable of dynamic spectrum access require frequency agile transmitters with a clean output spectrum. High-Q filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional Harmonic Rejection mixers suppress only a few harmonics. This paper presents an 8-path poly-phase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below -40dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over 3 octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared to 50% improves power upconverter efficiency. A transmitter realized in 0.16￭m CMOS works from 100-800MHz at a maximum single tone output power of 10.8dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is >21dBm, while the LO leakage and image rejection is better than -45dBc