On the non-termination of MDG-based abstract state enumeration

AbstractMultiway decision graphs are a new class of decision graphs for representing abstract states machines. This yields a new verification technique that can deal with the data-width problem by using abstract sorts and uninterpreted functions to represent data value and data operations, respectively. However, in many cases, it may suffer from the non-termination of the state enumeration procedure. This paper presents a novel approach to solving the non-termination problem when the generated set of states, even infinite, represents a structured domain where terms (states) share certain repetitive patterns. The approach is based on the schematization method developed by Chen and Hsiang, namely ρ-terms. Schematization provides a suitable formalism for finitely manipulating infinite sets of terms. We illustrate the effectiveness of our method by several examples

Term ordering problem on MDG

As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) designs. However, in some cases, MDG-based verification suffers from the state explosion problem. Some of cases are caused by the standard order used by MDG to order cross-terms that have the same top-level function symbol. These terms usually label decision nodes and must be ordered. We call this kind of state explosion the standard term ordering problem. A solution based on function renaming and cross-term rewriting is proposed in this paper. Experimental results show that this solution can solve the problem completely and thus increase the range of circuits that can be verified by MDG

Gate-Level Timing Verification Using Waveform Narrowing

We present a novel gate-level timing verification method that determines if a combinational circuit satisfies a maximal or a minimal required propagation delay. It is based on computing the greatest fixpoint over a set of equations derived from the gate forward and partial inverse functions, and their interconnections, in the domain of sets of (abstract) waveforms. False negative results can be obtained, however, these can be refined by limited case analysis (based on the analysis of reconvergent fanout). The resolution method is independent of the circuit delay model used, transition or floating mode; only the initial set of waveforms on the primary inputs distinguishes them. The method can accommodate interval gate delays, separate rise and fall transition delays, and component delay correlation. 1. Introduction The function of a static timing verifier is to ascertain that timing constraints such as set-up and hold times on flip-flops are satisfied in the range of operating clock f..

Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints

The determination of the maximum time separations of events is important in the design, synthesis, and verification of digital systems, especially in interface timing verification. Many researchers have explored solutions to the problem with various restrictions: a) on the type of constraints, and b) on whether the events in the specification are allowed to occur repeatedly. When the events can occur only once, the problem is well solved. There are fewer concrete results for systems where the events can occur repeatedly. We extend the work by Hulgaard et al. for computing the maximum separation of events in cyclic constraint graphs with latest constraints to constraint graphs with both linear and latest constraints

Verification methodology manual for SystemVerilog

SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. This book is based upon best verification practices by ARM, Synopsys and their customers. It is useful for those involved in the design or verification of a complex chip