Machine division

Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.Board of Regents, University of Texas Syste

Data tag control for quantum-dot cellular automata

The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.Board of Regents, University of Texas Syste

Memristor logic design using driver circuitry

A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.Board of Regents, University of Texas Syste

Modular pipeline fast Fourier transform

A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline √{square root over (N)} point fast Fourier transform (FFT) modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFTs, the modular pipeline FFT maintains the bandwidth of existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.Board of Regents, University of Texas Syste

Ultra high-speed transaxial image reconstruction of the heart, lungs, and circulation via numerical approximation methods and optimized processor architecture

A high temporal resolution scanning multiaxial tomography unit, the Dynamic Spatial Reconstructor (DSR), presently under development will be capable of recording multiangular X-ray projection data of sufficient axial range to reconstruct a cylindrical volume consisting of up to 240 contiguous 1-mm thick cross sections encompassing the intact thorax. At repetition rates of up to 60 sets of cross sections per second, the DSR will thus record projection data sufficient to reconstruct as many as 14 400 cross-sectional images during each second of operation. Use of this system in a clinical setting will be dependent upon the development of software and hardware techniques for carrying out X-ray reconstructions at the rate of hundreds of cross sections per second. A conceptual design, with several variations, is proposed for a special purpose hardware reconstruction processor capable of completing a single cross section reconstruction within 1 to 2 msec. In addition, it is suggested that the amount of computation required to execute the filtered back-projection algorithm may be decreased significantly by the utilization of approximation equations, formulated as recursions, for the generation of internal constants required by the algorithm. The effects on reconstructed image quality of several different approximation methods are investigated by reconstruction of density projections generated from a mathematically simulated model of the human thorax, assuming the same source-detector geometry and X-ray flux density as will be employed by the DSR. These studies have indicated that the prudent application of numerical approximations for the generation of internal constants will not cause significant degradation in reconstructed image quality and will in fact require substantially less auxiliary memory and computational capacity than required by direct execution of mathematically exact formulations of the reconstruction algorithm.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/23631/1/0000595.pd

System design with memristor technologies

System Design with Memristor Technologies explores design solutions for memristors, covering research and development trends in memristor technology, fabrication, modelling, and applications, and the design and implementation of arithmetic units using memristors

Dual-path fused floating-point two-term dot product unit

A fused floating-point dot product unit. The fused dot product unit includes an improved alignment scheme that generates smaller significand pairs compared to the traditional alignment due to the reduced shift amount and sticky logic. Furthermore, the fused dot product unit implements early normalization and a fast rounding scheme. By normalizing the significands prior to the significand addition, the length of the adder can be reduced and the round logic can be performed in parallel. Additionally, the fused dot product unit implements a four-input leading zero anticipation unit thereby reducing the overhead of the reduction tree by encoding the four inputs at once. The fused floating-point dot product unit may also employ a dual-path (a far path and a close path) algorithm to improve performance. Pipelining may also be applied to the dual-path fused dot product unit to increase the throughput.Board of Regents, University of Texas Syste

Data tag control for quantum-dot cellular automata

The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.Board of Regents, University of Texas Syste

Memristor-based adders using memristors-as-drivers (MAD) gates

Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Board of Regents, University of Texas Syste