VERIS: An efficient model checker for synchronous VHDL designs

in this paper a solution for property verification of synchronous VHDL designs is introduced, and an efficient symbolic model checker is implemented. The model checker applies the feature of synchronous circuit design and the locality feature of property to reduce the size of the state space of the internal finite state machine (FSM) model, thus speeding up the reachability analysis and property checking of circuits. A counterexample generation mechanism is also implemented. We have used the implemented model checker to verify several benchmark circuits; the experimental results contrast with another well-known model checker and demonstrate that our solution is more practicable