Optimization of Enzymatic Biochemical Logic for Noise Reduction and Scalability: How Many Biocomputing Gates Can Be Interconnected in a Circuit?

We report an experimental evaluation of the "input-output surface" for a biochemical AND gate. The obtained data are modeled within the rate-equation approach, with the aim to map out the gate function and cast it in the language of logic variables appropriate for analysis of Boolean logic for scalability. In order to minimize "analog" noise, we consider a theoretical approach for determining an optimal set for the process parameters to minimize "analog" noise amplification for gate concatenation. We establish that under optimized conditions, presently studied biochemical gates can be concatenated for up to order 10 processing steps. Beyond that, new paradigms for avoiding noise build-up will have to be developed. We offer a general discussion of the ideas and possible future challenges for both experimental and theoretical research for advancing scalable biochemical computing

A Real Time Tax Smoothing Based Fiscal Policy Rule

In this paper we consider the real-time implementation of a fiscal policy rule based on tax smoothing (Barro (1979) and Bohn (1998)). We show that the tax smoothing approach, augmented by fiscal habit considerations, provides a surprisingly accurate description of US budget surplus movements. In order to investigate the robustness of the policy implications of the rule, we construct a real-time US fiscal data set, complementing the data documented by Croushore and Stark (2001). For each variable we record the different vintages, reflecting the remeasurements that occur over time. We demonstrate that the easily constructed rule provided a useful benchmark for policy analysis that is robust to real-time remeasurements.fiscal rules, tax smoothing, fiscal habits, real-time data

A reconfigurable hardware membrane system

Abstract P systems are massively parallel systems and software simulations do no usually allow to exploit this parallelism. We present a parallel hardware implementation of a special class of membrane systems. The implementation is based on a universal membrane hardware component that allows to efficiently run membrane systems on specialized hardware such as FPGAs. The implementation is presented in detail as well as performance results and an example.