A DfT Architecture for Asynchronous Networks-on-Chip

International audienceThe Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANOC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also give

How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes

International audienceThe Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented

A three-level signature by graph for Reverse Engineering of mechanical assemblies

Several approaches exist to provide Reverse Engineering solutions on mechanical parts. Mechanical assemblies and the expertise information retrieved at the same time with the model geometry are not really taken into account in the literature. Thus, the main challenge of this contribution is to propose a methodology to retrieve the Digital Mock-Up of a mechanical assembly from its meshed data (from digitalization). The output DMU consists of expertise information and parameterized CAD models. The methodology proposed relies on a signature by a three-level graph. It enables to provide an adequate level of details by identifying the corresponding functional surfaces in meshed data. The first-level graph is a connectivity graph; the intermediate level is the same as the first with the geometric type of face added to each node (plane, cylinder and sphere) and the deepest level corresponds to a precedence graph. This one provides information such as functional surfaces and position between them (perpendicularity, coaxiality etc.). The solutions developed and the results are presented in this paper. The methodology is illustrated thanks to an industrial use-case with a scan of an assembly with a connecting rod and a piston. The conclusion and perspectives will complete this paper

Towards new processes to reverse engineering digital mock-ups from a set of heterogeneous data

Reverse-Engineering techniques are commonly used to generate or update the CAD model of a single physical object. However, the reverse engineering of a whole assembly is still very tedious and time-consuming. This is mainly due to the fact that the complete definition of the final digital mock-up relies on the integration of multiple sources of heterogeneous data, such as point clouds, images, schemes or any type of digital representations which are not yet fully supported by actual software. Thus, having new methods and tools to better process and integrate those multi-representations would speed up the reconstruction process which could therefore become adapted to the reconstruction of large mechanical assemblies such as in automotive field. This paper addresses such a difficult problem. Actually, starting from an analysis of three different use-cases, we first highlight the lack of software solutions for the considered problematic. Then, the proposed process-workflow is introduced together with the advanced mechanisms involved in the reconstruction. In our approach, the signatures of the components play a key role in the identification of the relationships and matching procedures between the heterogeneous data. This process-workflow is illustrated on an example in the automotive domain

A three-level signature by graph for Reverse Engineering of mechanical assemblies

Several approaches exist to provide Reverse Engineering solutions on mechanical parts. Mechanical assemblies and the expertise information retrieved at the same time with the model geometry are not really taken into account in the literature. Thus, the main challenge of this contribution is to propose a methodology to retrieve the Digital Mock-Up of a mechanical assembly from its meshed data (from digitalization). The output DMU consists of expertise information and parameterized CAD models. The methodology proposed relies on a signature by a three-level graph. It enables to provide an adequate level of details by identifying the corresponding functional surfaces in meshed data. The first-level graph is a connectivity graph; the intermediate level is the same as the first with the geometric type of face added to each node (plane, cylinder and sphere) and the deepest level corresponds to a precedence graph. This one provides information such as functional surfaces and position between them (perpendicularity, coaxiality etc.). The solutions developed and the results are presented in this paper. The methodology is illustrated thanks to an industrial use-case with a scan of an assembly with a connecting rod and a piston. The conclusion and perspectives will complete this paper

Le «torculus spécial». Comparaison entre le manuscrit 121 de la Bibliotheque d'Einsiedeln en Suisse et le manuscrit latin 903 de la Bibliotheque Nationale de Paris ou Graduel de Saint-Yrieix

[FR] Le "torculus spécial" est un neume de trois notes don!la premiére est un son flou, léger, les deux autres sons étant élargis. Ce torculus. dans les manuscrits anciens du Sud de la Chrétienté, perd sa premiére note et devient ainsi une clivis.Pour notre étude, nous avons comparé le manuscrit 121 de la Bibliothéque d'Einsiedeln en Suisse, Graduel du XI siécle, au manuscrit latin 903 de la Bibliothéque Nationale de Paris ou Graduel de Saint-Yrieix, du Sud de la France, également du XI siécle. Notre enquete nous a révélé 288 cas que l'on a répartis en quatre groupes: l.) le torculus d'intonation: 78 cas; 2.) le torculus de passage: 66 cas; 3.) le torculus sur finale de mot: 114 cas; 4.') trente exemples hors catégorie. Pour enrichir notre travail, nous avons ensuite introduit le témoignage d'autres Gra­duels figurant parmi les plus importants monuments du chant grégorien. On a pu constater que si les pays germaniques gardent toujours les trois notes (le torculus), Saint-Yrieix n'en a toujours que deux (la clivis). Quant aux autres manuscrits, c'est tantôt l'un, tantôt l'autre.Peer reviewe

How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes

The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented. 1

Towards new processes to reverse engineering digital mock-ups from a set of heterogeneous data

Reverse-Engineering techniques are commonly used to generate or update the CAD modelof a single physical object. However, the reverse engineering of a whole assembly is still verytedious and time-consuming. This is mainly due to the fact that the complete definition of thefinal digital mock-up relies on the integration of multiple sources of heterogeneous data, suchas point clouds, images, schemes or any type of digital representations which are not yet fullysupported by actual software. Thus, having new methods and tools to better process andintegrate those multi-representations would speed up the reconstruction process which couldtherefore become adapted to the reconstruction of large mechanical assemblies such as inautomotive field. This paper addresses such a difficult problem. Actually, starting from ananalysis of three different use-cases, we first highlight the lack of software solutions for theconsidered problematic. Then, the proposed process-workflow is introduced together with theadvanced mechanisms involved in the reconstruction. In our approach, the signatures of thecomponents play a key role in the identification of the relationships and matching proceduresbetween the heterogeneous data. This process-workflow is illustrated on an example in theautomotive domain

High-Speed Design-for-Test Architecture for Asynchronous NoC-based Systems-on-Chip

International audienc

La télémédecine en zones rurales : représentations et expériences de médecins généralistes

International audienceIntroduction : La télémédecine constitue une nouvelle forme de pratique médicale dont le développement est aujourd’hui en pleine expansion. Elle trouve un écho particulier dans certains territoires lorrains où le déficit en médecins généralistes et spécialistes nécessite le développement de nouvelles formes de pratiques. L’objectif de cette étude était d’explorer les représentations de la télémédecine, et de la téléconsultation en particulier, des médecins généralistes exerçant en zones déficitaires en offre de soins en Lorraine et d’identifier les avantages et désavantages perçus de son développement.Méthodes : Une analyse qualitative a été faite à partir de cinq focus groupes réalisés avec 32 médecins entre juin 2014 et juillet 2015 dans un territoire à faible densité médicale.Résultats : Cette étude montre qu’il existe une méconnaissance générale de la télémédecine. Les médecins expriment leur désir de préserver leur rôle de pivot et d’être acteurs de cette télémédecine qui ne devra pas leur être imposée. Les réticences en termes d’aspects juridiques et financiers sont des freins à son développement. Enfin, la télémédecine devra respecter un cadre légal en termes de responsabilité médicale et de sécurisation des données.Discussion : Chaque mois, plus de cent actes de télémédecine sont réalisés en Lorraine. Bien qu’il s’agisse d’une solution permettant de faciliter l’accès aux soins dans les zones déficitaires, les médecins semblent vouloir préserver leur relation médecin-patient et ne se sentent pas prêts à modifier leur pratique