DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been demonstrated as one of the most promising candidates due to its endurance and compatibility. However, the integration density of SRAM-based PIM is much lower than other non-volatile memory-based ones, due to its inherent 6T structure for storing a single bit. Within comparable area constraints, SRAM-based PIM exhibits notably lower capacity. Thus, aiming to unleash its capacity potential, we propose DDC-PIM, an efficient algorithm/architecture co-design methodology that effectively doubles the equivalent data capacity. At the algorithmic level, we propose a filter-wise complementary correlation (FCC) algorithm to obtain a bitwise complementary pair. At the architecture level, we exploit the intrinsic cross-coupled structure of 6T SRAM to store the bitwise complementary pair in their complementary states ($Q/\overline{Q}$), thereby maximizing the data capacity of each SRAM cell. The dual-broadcast input structure and reconfigurable unit support both depthwise and pointwise convolution, adhering to the requirements of various neural networks. Evaluation results show that DDC-PIM yields about $2.84\times$ speedup on MobileNetV2 and $2.69\times$ on EfficientNet-B0 with negligible accuracy loss compared with PIM baseline implementation. Compared with state-of-the-art SRAM-based PIM macros, DDC-PIM achieves up to $8.41\times$ and $2.75\times$ improvement in weight density and area efficiency, respectively.Comment: 14 pages, to be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD

Defect Contour Detection of Complex Structural Chips

In the manufacture of chips, it is important to detect defects to assess whether the chip is potentially damageable that could cause unnecessary cost. Most assessment rules are set in light of characteristics determined by defect contours, such as area and range. However, conventional image process methods seldom show a satisfactory performance on chips with complex structures because they are difficult to distinguish defect contours from edges of structures. To solve this issue, this study proposes a method based on region segmentation search. The positions of structures in the image are calculated by edge matching to obtain the number of structure layers in each pixel. Regions whose pixels have the same number are divided into subregions which are coded by the two-pass algorithm. The edges in each subregion are then extracted by the Canny operator to construct edge information of the whole image. Interpolation is used to correct incomplete defect edges according to their endpoints. The remaining interference contours are eliminated on the basis of their shapes. A study of a certain kind of chips is presented. Different illumination situations were simulated to verify the robustness of the proposed method. Most bubbles in the images were detected successfully with their contours coded accurately. Because of this, more than 92% of assessment results of chips were identical to the ones in reality engineering, which proves that the method proposed by this study can efficiently detect the defect contours and improve the ability obviously relative to the current approaches