Hardware synthesis of high-level C constructs

In this paper, experiments with a useable C frontend for the CCC behavioural synthesis tools are presented and analysed. This tool combination is able to rapidly deliver provably-correct hardware implementations at the RTL level, from high-level, abstract, algorithmic executable specifications at the C program level. The used constructs are discussed and a number of experiments with the tool are outlined and evaluated. The contribution of the CCC tools are invaluable for implementing real-life applications in hardware involving models with complex control flow and rich in loops and arrays. The discussed experiments prove the tools useable. © 2015 ACM

Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework

Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive optimization schemes in order to satisfy hardware implementation requirements. Meanwhile, commercial tools like Xilinx VivadoHLS or, more recently, Compiler-driven code optimizations, are a useful means to improve quality of automatically generated hardware implementations. Such optimizations include loop transformations. Some of the most important transformations are loop unrolling and loop pipelining, which when they are combined with careful instruction reordering, deliver highly optimized schedules. Amongst others, instruction dependencies are significant limitations in loop optimization. In this paper, we discuss possible resolutions of loop pipelining issues such as dealing with dependencies between loop body operations. This has a great impact on high-level synthesis. Results from experiments with several benchmarks on the CustomCoprocessorsCompiler and VivadoHLS tools demonstrate that CustomCoprocessorsCompiler can deliver better output than VivadoHLS. © 2018 IEEE

Global and Pointer Variables in High-Level Synthesis

High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like accelerators or coprocessors. However, many high-level language characteristics have not been ported in such tools, under the false assumption that HLS programmers have a good understanding of hardware and of how actual circuits operate. This work is concentrated on the use of global and static variables in HLS. Such variables are often not allowed in HLS tools, since their storage class makes their support difficult. We will present an intelligent global and static variable placement methodology, which attempts to nullify the negative effects of supporting such variables, by carefully selecting variables to be placed globally, within an appropriate memory module. Addressing of such a module is direct, which allows the use of static pointers in the input high-level language code. We have implemented our methodology in the CCC HLS tool, and tested it with various benchmarks of varying complexity. We have also tested the same benchmarks with other popular HLS tools, and we show that under a fair comparison, CCC produces equal, or in some cases superior output to other tools with regard to global and static variable support. © 2020 IEEE

Loop pipelining in high-level synthesis with CCC

High-level synthesis allows the use of high-level programming languages for hardware design. Traditional programming with the C and ADA languages can lead to efficient hardware description through recently developed high-level synthesis tools. Compilers play an important role in this process, since they can bridge differences between software programming and hardware design methodologies, thus making high-level synthesis tools better accepted by the scientific community. Furthermore, modern compiler optimizations can be employed in order to obtain optimal hardware descriptions. Loop transformations are often the focus of compiler optimizations, since they can result in significant performance improvement, for both software and hardware programming. In this paper, we discuss the implementation of loop pipelining in the front-end compiler of the CCC high-level synthesis tool, and in particular we present new optimization techniques that lead to a decreased number of states in the FSM-based output of CCC. We present several experiments conducted on the Livermore loops and the MPEG2 open-source code, which prove the claimed improvement. © 2017 IEEE

Minimal-area loop pipelining for high-level synthesis with CCC

Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless, compiler optimizations can improve efficiency of automatically generated hardware descriptions and make high-level synthesis to become the dominant technology to build more complicated hardware as well. Compilers, well known and explored software tools, can allow programmers to use their software skills on hardware programming, without any language compromises. Furthermore, compiler optimizations transform the input code, in order to produce a high-quality high-performance output hardware description. In this paper, we discuss compiler issues for high-level synthesis, and in particular, the incorporation of loop pipelining in the C language front end of the CCC high-level synthesis tool. We also present a novel pipelining technique that minimizes the area used for the pipeline prologue and epilogue. Results from experiments on the Livermore loops and Mpeg2 open-source codes validate our technique. © 2017 TEI OF WESTERN MacEdonia

Operation Dependencies in Loop Pipelining for High-Level Synthesis

Research and industry interest in high-level synthesis has been renewed in the last few years, proven by the introduction of new tools or improved versions of existing tools. Academic tools like Gaut or CCC have recently appeared in new versions with expanded functionality in order to cover increased hardware design requirements. Likewise, industrial tools like Xilinx VivadoHLS or, more recently, Cadence Stratus have appeared and are continuously evolving in their effort to succeed in the market. One technology that high-level synthesis tools have chosen to invest on is compiler-driven code optimizations, which are a promising means to improve efficiency of automatically generated hardware. Loop transformations are among the most popular compiler optimizations, for both software and hardware targets. Loop unrolling and loop pipelining, coupled with careful instruction reordering, can deliver highly optimized output. Instruction dependencies play a significant role in such optimizations, limiting performance improvement for the final code. In this paper, we discuss the issue of dependencies among loop body operations, especially those forming cycles, and their impact on high-level synthesis. We present results from experiments with several benchmarks on the CCC and VivadoHLS tools, showing that CCC can deliver better output than VivadoHLS in the presence of complex operation dependence cycles. © 2018 Tei of Western Macedonia

Variations on a Connectivity-based Legalizer for Standard Cell Design

Legalization is considered the most significant step in a placement correlated standard cell design flow as moving cells towards legal positions to avoid overlap among them may escalate the overall wire length. Monolithic legalizers, that is i.e., legalizers that do not partake in global placement, should take into account the connectivity between cells, in order to generate a final result with the minimum quality loss. In this paper we present a set of variations on a connectivity-based legalization scheme, that produce notable results, based on minor modifications that target total interconnection wire length and the design specifications concerning density limitations. © 2021 IEE