Monitoring the electrical properties of the back silicon interface of silicon-on-sapphire wafers

The density and the electrical nature of the interface traps at the silicon-sapphire interface of silicon-on-sapphire (SOS) MOSFETs have a significant influence on the electrical characteristics of these transistors. This letter describes a simple MOS test structure for evaluating the electrical properties of this interface of SOS wafers. Measurement and modeling of the C-V characteristics of the test structure fabricated on production SOS wafers are presented. We have demonstrated that the C-V characteristics are an efficient tool for studying the depletion of the silicon-sapphire interface by the interface trapped charge

Origin of the low frequency type curve in silicon-on-sapphire MOS capacitors

MOS capacitor C-V measurement is a standard tool for investigating the electrical properties of a wafer. This paper investigates the use of a novel MOS capacitor structure for use with thin film silicon-on-sapphire wafers in order to determine backs surface silicon-sapphire interface quality