A new design methodology of highly reliable TFT based integrated circuits in display applications

Thin-film transistors (TFTs) technology is currently the dominant technology for pixel switching in display application. The new consumer electronics requires higher resolution and brightness, lower power consumption, multi-functional with new features such as flexible and foldable display. This drives TFT devices to deliver more complex functions. Owing to a sustained, enormous effort in TFT research and development and a continuous capital investment from the display industry around the world for the past three decades, the performance of TFT has not only surpassed the display requirements in most areas, but also go beyond the simply switch to more complex digital and analogue integrated circuits, for example, the flexible and narrow bezel displays integrated row drivers with TFT technology next to the pixel array. Such integrated circuits comprise thousands of switches operating together, requires an accurate analysis during design. In the recent years, new display technologies, such as organic light-emitting diode (OLED) display and light-emitting diode (LED) displays have been emerging and become commercial reality due to certain advantages like self-luminous, high contrast, and etc. However, the OLED device has relative shorted lifetime and the current driving TFTs typically suffer from the electrical instability issue under high temperature and long-time stress condition. Thus, the reliability concerns in display have generated a considerable number of experimental studies and require careful analysis for the design of its pixel and integrated drivers. Particularly, individual TFTs are exposed to various stress condition in display operation with different degradation such as threshold voltage shift (ΔVth) or mobility (μ) decreasing result in a failure of display operation, given that the performance of an aging TFT might deviate from expectation of original design, and moreover, it might influence its neighboring TFTs. Traditional design method considering device performance variation and device-level aging approach of ΔVth and μ may not appropriate given that the traditional design of display pixel and driver circuit did not consider the evolutionary effects to each TFTs and different aging rate under various stress condition. Please click Additional Files below to see the full abstract

Learning to Rank Question Answer Pairs with Holographic Dual LSTM Architecture

We describe a new deep learning architecture for learning to rank question answer pairs. Our approach extends the long short-term memory (LSTM) network with holographic composition to model the relationship between question and answer representations. As opposed to the neural tensor layer that has been adopted recently, the holographic composition provides the benefits of scalable and rich representational learning approach without incurring huge parameter costs. Overall, we present Holographic Dual LSTM (HD-LSTM), a unified architecture for both deep sentence modeling and semantic matching. Essentially, our model is trained end-to-end whereby the parameters of the LSTM are optimized in a way that best explains the correlation between question and answer representations. In addition, our proposed deep learning architecture requires no extensive feature engineering. Via extensive experiments, we show that HD-LSTM outperforms many other neural architectures on two popular benchmark QA datasets. Empirical studies confirm the effectiveness of holographic composition over the neural tensor layer.Comment: SIGIR 2017 Full Pape

The electro production of d* dibaryon

$d^*$ dibaryon study is a critical test of hadron interaction models. The electro production cross sections of $ed\to ed^*$ have been calculated based on the meson exchange current model and the cross section around 30 degree of 1 GeV electron in the laboratory frame is about 10 nb. The implication of this result for the $d^*$ dibaryon search has been discussed.Comment: 12 pages, 12 figures, Late

Classification of Bipartite and Tripartite Qutrit Entanglement under SLOCC

We classify biqutrit and triqutrit pure states under stochastic local operations and classical communication. By investigating the right singular vector spaces of the coefficient matrices of the states, we obtain explicitly two equivalent classes of biqutrit states and twelve equivalent classes of triqutrit states respectively.Comment: 10 page

Non-Abelian Quantum Hall States and their Quasiparticles: from the Pattern of Zeros to Vertex Algebra

In the pattern-of-zeros approach to quantum Hall states, a set of data {n;m;S_a|a=1,...,n; n,m,S_a in N} (called the pattern of zeros) is introduced to characterize a quantum Hall wave function. In this paper we find sufficient conditions on the pattern of zeros so that the data correspond to a valid wave function. Some times, a set of data {n;m;S_a} corresponds to a unique quantum Hall state, while other times, a set of data corresponds to several different quantum Hall states. So in the latter cases, the patterns of zeros alone does not completely characterize the quantum Hall states. In this paper, We find that the following expanded set of data {n;m;S_a;c|a=1,...,n; n,m,S_a in N; c in R} provides a more complete characterization of quantum Hall states. Each expanded set of data completely characterize a unique quantum Hall state, at least for the examples discussed in this paper. The result is obtained by combining the pattern of zeros and Z_n simple-current vertex algebra which describes a large class of Abelian and non-Abelian quantum Hall states \Phi_{Z_n}^sc. The more complete characterization in terms of {n;m;S_a;c} allows us to obtain more topological properties of those states, which include the central charge c of edge states, the scaling dimensions and the statistics of quasiparticle excitations.Comment: 42 pages. RevTeX