Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Degradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization

Novel TCAD Approach for the Investigation of Charge Transport in Thick Amorphous SiO2 Insulators

A TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal-insulator-metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping-detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach

Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation

In this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal

Experimental analysis and electro-thermal simulation of low- and high-voltage ESD protection bipolar devices in a Silicon-On-Insulator Bipolar-CMOS-DMOS technology

We present the results of extensive characterization of fully isolated SOI NPN bipolar protection devices by means of both 2D simulations, DC and TLP measurements, and HBM/TLP ESD stress tests. Excellent agreement between measured and simulated quasistatic and pulsed I-V characteristics of the protection structures has been obtained. We also confirm the usefulness of 2D/3D device simulations for ESD optimization

Constant-current time dependent dielectric breakdown in thick amorphous SiO2 capacitors

Charge transport in thick amorphous silicon dioxide capacitors for integrated galvanic insulators is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. The material intrinsic defectivity and the large biases applied to such devices give rise to a leakage current which is responsible of degradation and failure. Hence it is crucial to have a complete understanding of the charge-transport main physical mechanisms in amorphous silicon oxide. For this reason, constant-current time dependent dielectric breakdown measurements have been performed on thick metal-insulator-metal structures and, in order to gain insight on the role of defects on breakdown, numerical simulations have been compared to experiments

Characterization and numerical analysis of breakdown in thick amorphous SiO2 capacitors

Charge transport in thick amorphous silicon dioxide capacitors for integrated galvanic insulators is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. The material intrinsic defectivity and the large biases applied to such devices give rise to a leakage current which is responsible for degradation and failure. Hence it is crucial to have a complete understanding of the charge-transport main physical mechanisms in amorphous silicon oxide. In particular, charge injection at contacts and charge build-up due to trapping/de-trapping mechanisms in the bulk of the oxide are expected to play a crucial role and their complex coupled interaction needs to be investigated via a TCAD-based approach. For this reason, time-dependent dielectric breakdown measurements at constant-current stresses and voltage-ramp stresses up to breakdown have been performed on thick metal-insulator–metal structures, and numerical simulations have been carried out so to predict the failure mechanisms. To this purpose, special attention has been devoted to the physical modeling of defects and impact-ionization generation

Peripheral Nanostructured Porous Silicon Boosts Static and Dynamic Performance of Integrated Electronic Devices

Nanomaterials hold the promise of revolutionizing electronics and, in turn, its applications, thanks to the unique properties of charge carriers traveling in structures with length scale down to a few nanometers. Here, the tremendous reduction of mobility and lifetime of charge carriers when traveling in randomly arranged nanostructured silicon crystallites, namely, nanostructured porous silicon (n-PSi), is leveraged to simultaneously improve the turn-off switching speed and reverse operation voltage of solid-state devices integrated nearby. As a proof-of-concept application, it is shown that the integration of peripheral n-PSi next to solid-state diodes fabricated by an industrial process, namely, PSi-nanostructured diodes, reliably improves both the breakdown voltage (>2× increase) and switching time (30% reduction), with respect to those of reference diodes without n-PSi, with no significant drawbacks on other diode parameters. This effect is shown to be robust with respect to n-PSi preparation conditions and diode architectures, thus paving a new way toward groundbreaking n-PSi applications in microelectronics

Anomalous increase of leakage current in epoxy moulding compounds under wet conditions

An interdigitated capacitor embedded in the EMC has been realized and characterized under controlled humidity conditions by applying a DC step voltage and monitoring the leakage current as a function of time. Both experimental characterization and TCAD simulations of dry and wet EMC samples have been carried out to fully understand the involved charge transport mechanisms. The anomalous increase of current with time in wet conditions is explained assuming a build-up of space charge directly induced by the high-injection at the metal electrodes. The assumption is confirmed by TCAD simulations

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device

TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors

A combined experimental and simulation analysis of the degradation mechanisms induced by hot carriers in a silicon-based split-gate n-channel LDMOS transistor featuring an STI structure is reported. In this regime, electrons can gain sufficient kinetic energy necessary to create charged traps at the silicon/oxide interface, thus inducing device degradation and causing the shift of the electrical parameters of the device. In particular, the on-resistance degradation in linear regime has been experimentally characterized at different stress conditions and at room temperature. The hot-carrier degradation has been reproduced in the frame of TCAD simulations by using physical-based models aimed at reproducing the degradation kinetics. An investigation of the electron distribution function at different stress conditions and its dependence on the split-gate bias is carried out achieving a quantitative understanding of the role played by hot electrons in the hot-carrier degradation mechanisms of the device under test