Fast and Efficient Dataflow Graph Generation

International audienceDataflow modeling is a highly regarded method for the design of embedded systems. Measuring the performance of the associated analysis and compilation tools requires an efficient dataflow graph generator. This paper presents a new graph generator for Phased Computation Graphs (PCG), which augment Cyclo-Static Dataflow Graphs with both initial phases and thresholds. A sufficient condition of liveness is first extended to the PCG model. The determination of initial conditions minimizing the total amount of initial data in the channels and ensuring liveness can then be expressed using Integer Linear Programming. This contribution and other improvements of previous works are incorporated in Turbine, a new dataflow graph generator. Its effectiveness is demonstrated experimentally by comparing it to two existing generators, DFTools and SDF3

A Signal Flow Graph Approach to the Resolution of Spherical Triangles Using CORDIC

Jack Volder’s original motivation for the COordinate DIgital Computer (CORDIC) was the real-time digital solution of spherical triangle equations employed in airborne navigation, for which he presented a solution flow diagram without detailing its construction. In fact, without a strong guidance, it is not easy to express the solutions of linear algebraic problems such as those involved when solving spherical triangles as cascades of CORDIC operations—called by Volder CORDIC solution-flow diagrams—and thus to devise a system solution on CORDIC processing units. As it gives a bird’s eye view of the system design problem, a signal flow graph representation of the underlying system of linear equations provides such guidance; the operations leading to the problem solution are uncovered by performing a sequence of partial flow reversals on the graph. The approach is illustrated by the problem where two sides and the included angle of a spherical triangle are given, called SAS problem, that is encountered in applications as diverse as air navigation, lattice filters for adaptive processing, and dexterous robotic hands. The solutions thus obtained are at least as efficient as existing ones, whenever available

Decision Guide Environment for Design Space Exploration

International audienceIn current embedded system design practice, only few architectural solutions and mappings of the functionalities of a system on the architecture's components are examined. This paper presents an optimization-based method and the associated tool developed to help designers take architectural decisions. The principle of this approach is to efficiently explore the design space and to dynamically provide the user with the capabilities to visualize the evolution of selected criteria. The first objective is solved by developing an enhanced version of the adaptive simulated annealing algorithm. Since the method is iterative, multiple solutions may be examined and the tool lets the user stop exploration at any time, tune parameters and select solutions. Moreover we present an approach for systems whose functionalities are specified by means of multiple models of computation, in order to handle descriptions of digital signal applications at several levels of detail. The tool has been applied to a motion detection application in order to determine architectural parameters

Méthodes d'optimisation pour le partitionnement logiciel/matériel de systèmes à description multi-modèles

La complexité des systèmes embarqués, l'hétérogénéité de leur spécification et la nécessité de les concevoir et de les produire à moindre coût motivent l'introduction d'outils d'aide à la conception au niveau système. Cette thèse traite du partitionnement logiciel/matériel, qui consiste à définir l'architecture du système (processeurs, circuits dédiés, mémoires, ...) et à affecter les traitements aux processeurs et aux circuits. Ce problème est formulé comme un problème d'optimisation dont l'objectif est de minimiser le coût global du système. En utilisant une méthode de recherche locale et en construisant un environnement permettant d'intégrer facilement de nouveaux modèles de traitement et de composants de l'architecture, on montre qu'il est possible d'obtenir des solutions proches de l'optimum pour des spécifications hétérogènes (DFG, flots de données synchrones). L'efficacité est obtenue en accélérant une version rapide du recuit simulé et en la rendant plus facile à utiliser.The complexity of embedded systems, the heterogeneity of their specification and the need to design and manufacture them at the lowest cost motivate the introduction of CAD tools at the system level. This thesis deals specifically with hardware/software partitioning, i.e. defining the architecture of the system (processors, ASICs, memory, etc.) and assigning the computations to the processors and dedicated ICs. This problem is formulated as an optimization problem whose objective is the minimization of the global cost of the system. By using a local search method and by building an environment that enables easy integration of new models of computation and of novel architectural components, we show how to reach solutions close to the global optimum for heterogeneously specified systems (DFG, SDF, etc.). Efficiency is achieved by starting with a fast version of simulated annealing, improving further on its speed and reducing parameter tuning to a minimum.EVRY-BU (912282101) / SudocVILLEURBANNE-DOC'INSA LYON (692662301) / SudocSudocFranceF

Approche calculatoire pour la déconvolution en aveugle (application à l'imagerie SIMS)

La Spectroscopie de Masse d'Ions Secondaires (SIMS) permet d'obtenir des images de distributions d'atomes à la surface d'un échantillon. La réponse impulsionnelle (RI) de l'instrument est inconnue. La déconvolution en aveugle a pour but d'enlever le flou associé. Ce problème mal conditionné est résolu en contraignant sa solution (régularisation). Le degré optimum de régularisation dépend d'un paramètre à déterminer. Il est trouvé, ainsi que ceux de la RI, par la méthode de validation croisée généralisée. Une étape de calibrage restreint l'espace de recherche des paramètres de la RI et les calculs sont accélérés en exploitant le modèle gaussien. L'image est déconvoluée en résolvant un grand système linéaire par la méthode du gradient conjugué. Un préconditionnement exploitant la séparabilité de la RI (isotrope ou anisotrope) en accélère la convergence. On montre comment utiliser plusieurs images d'un échantillon pour avoir une résolution plus fine (super-résolution).Secondary Ion Mass Spectrometry (SIMS) creates images of atomic distributions on a sample's surface. The point spread function (PSF) is unknown. Blind deconvolution is used to remove the associated blur. This ill-conditionned problem is solved by constraining its solution (regularization). The optimum degree of regularization depends on a parameter to be determined. This parameter is found, as well as those of the PSF, by the generalized cross validation method. A calibration phase reduces the search space for the PSF parameters. The gaussian model used for the PSF is exploited to accelerate the computations. The image is deconvolved by solving a large linear system with the conjugate gradient method. A preconditionner making use of the PSF separability (isotropic or anisotropic) speeds up convergence.EVRY-Bib. électronique (912289901) / SudocSudocFranceF

Design Space Exploration for Dynamically Reconfigurable Architectures

International audienceBy incorporating reconfigurable hardware in embedded system architectures it has become easier to satisfy the performance constraints of demanding applications while lowering system cost. In order to evaluate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an application must be assigned to the computing resources of the architecture: programmable processors and reconfigurable FPGA, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel design exploration tool - based on a local search algorithm with global convergence properties - which simultaneously explores choices for computing resources, assignments of nodes to these resources, task schedules on the programmable processors and context definitions for the reconfigurable circuits. The tool finds a solution that minimizes system cost while meeting the performance constraints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds accordingly a solution with close-to-minimal cost

Partitioning for Array Processors

This paper proposes a systematic method for mapping algorithms into fixed size array processors, in using the usual projection followed by a partioning. The paper is organised as following: section 2 presents the general principles of the partitioning used and the qualities of a good partitioning. Sections 3 and 4 introduce the mathematical tools needed to understand the next sections which present a method for mapping a n-dimensional domai

Conception de circuits à signaux mixtes pour des communications portables à basse tension et haute fréquence en CMOS bulk et SOI

Deep sub-micron CMOS technologies allow a very good integration of mocroelectronics circuits, as well as an increase of the implemented functions and speed of computations. At the same time, the problems created by parasitic effects and process fluctuations are an issue to be taken into consideration. New CMOS processes have been developed such as triple-well and silicon-on-insulator (SOI); they offer the freedom to isolate functional blocks in integrated circuits in separate islands, and therefore to have better control of the power consumption and of the circuit performance. Due to these technologies it is possible to tune some intrinsic parameters of the transistors, like threshold voltage or leakage current, by controlling the bulk/body of MOS transistors. A method for the threshold voltage control in deep-submicron triple-well 120 nm CMOS technology is described in this work; this process gives full access to the bulk of both transistors tyupes, NMOS and PMOS. This method can also be used for circuits implemented in PD-SOI processes. Two functionnal blocks, an operational amplifier and a threshold voltage mismatch VT monitor, have been developed for this application. This tchnique of threshold voltage control by body-biasing can be also used to diminish the parasitic effects caused by technology fluctuations on transistor parameters. RF circuits represent the second subjects of this research. Two frequency dividers have been realized in silicon-on-insulator (SOI) and bulk 90 nm CMOS; they reach an input frequency of 34 GHz and are supplied from a 1 V voltage source. Using the same method of VT control by body-biasing the circuit input sensitivity and the maximum input frequency can be tuned. The same approach has been applied in the case if a high-frequency quadrature voltage-controlled oscillator (VCO) where the transistor bulk is used as an external input for changing not only the transistors threshold voltage but also the oscillation frequency.EVRY-BU (912282101) / SudocSudocFranceF

An efficient simulated annealing schedule: implementation and evaluation

We present an implementation of an efficient general simulated annealing schedule and demonstrate experimentally that the new schedule achieves speedups often exceeding an order of magnitude when compared with other general schedules currently available in the literature. To assess the performance of simulated annealing as a general method for solving combinatorial optimization problems, we also compare the method with efficient heuristics on well-studied problems: the traveling salesman problem and the graph partition problem. For high quality solutions and for problems with a small number of close to optimal solutions, our test results indicate that simulated annealing outperforms the heuristics of Lin and Kernighan and of Karp for the traveling salesman problem, and multiple executions of the heuristic of Fiduccia and Mattheyses for the graph partition problem