Loss of thalamic serotonin transporters in early drug-naïve Parkinson’s disease patients is associated with tremor: an [123I]β-CIT SPECT study

In vitro studies revealed serotonin transporter (5-HTT) decline in Parkinson’s disease (PD). Yet, few studies investigated thalamic 5-HTT in vivo and its effect on PD heterogeneity. We analyzed thalamic [123I]β-CIT binding (mainly reflecting 5-HTT binding) in 32 drug-naïve PD patients and 13 controls with SPECT. Twenty-six patients were examined twice (17 months apart). Based on UPDRS scores, we identified subgroups of patients with moderate/severe tremor (PDT) and without tremor (PDWT) at the time of clinical diagnosis. Additionally, depressive symptoms were evaluated using the Beck Depression Inventory (BDI) at baseline. Mean thalamic specific to non-specific [123I]β-CIT binding ratio was lower in patients when compared to controls, and further decreased during follow-up. At baseline, average thalamic ratio was significantly lower in the PDT than in the PDWT subgroup. No correlation was found between BDI scores and thalamic binding ratios. Our findings show decline of [123I]β-CIT binding to thalamic 5-HTT in PD and its possible contribution to tremor onset

Asynchronous communication circuits : design, test, and synthesis

EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Charge-to-Digital Converter for Energy Harvesting Circuits Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy Harvesting Circuits

Energy harvesting generators deliver nondeterministic power density over a range of explicit environmental conditions. To mitigate the variability of power provided by the harvesters, this paper presents a novel energy-proportional design approach, in which the computational circuit is driven by input power so that its switching activity is a function of this power. Such an approach realizes an autonomous power gating, as the circuit starts to compute only when input power has arrived. We present a voltage sensor to exemplify the energy-proportional design principle, and such a sensor can be readily adopted in energy harvesting systems for on-chip dynamic power management. This sensor is driven by the charge from a capacitor that samples the measured input voltage to subsequently power up the asynchronous counter, which performs charge-to-digital conversion. We also present an analytical model that characterizes energy-proportional properties of the proposed voltage sensor. SPICE simulation results show that the proposed sensor design outperforms conventional voltage sensor circuits in terms of robustness and energy efficiency.

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b]

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b]

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers /

IX, 258 p. 150 illus.online resource