Analog programming of CMOS-compatible Al2_2O3_3/TiO2-x_\textrm{2-x} memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming

The exploration of memristors' behavior at cryogenic temperatures has become crucial due to the growing interest in quantum computing and cryogenic electronics. In this context, our study focuses on the characterization at cryogenic temperatures (4.2 K) of TiO$_\textrm{2-x}$-based memristors fabricated with a CMOS-compatible etch-back process. We demonstrate a so-called cryogenic reforming (CR) technique performed at 4.2 K to overcome the well-known metal-insulator transition (MIT) which limits the analog behavior of memristors at low temperatures. This cryogenic reforming process was found to be reproducible and led to a durable suppression of the MIT. This process allowed to reduce by approximately 20% the voltages required to perform DC resistive switching at 4.2 K. Additionally, conduction mechanism studies of memristors before and after cryogenic reforming from 4.2 K to 300 K revealed different behaviors above 100 K, indicating a potential change in the conductive filament stoichiometry. The reformed devices exhibit a conductance level that is 50 times higher than ambient-formed memristor, and the conduction drop between 300 K and 4.2 K is 100 times smaller, indicating the effectiveness of the reforming process. More importantly, CR enables analog programming at 4.2 K with typical read voltages. Suppressing the MIT improved the analog switching dynamics of the memristor leading to approximately 250% larger on/off ratios during long-term depression (LTD)/long-term potentiation (LTP) resistance tuning. This enhancement opens up the possibility of using TiO$_{\textrm{2-x}}$-based memristors to be used as synapses in neuromorphic computing at cryogenic temperatures

Hardware-aware Training Techniques for Improving Robustness of Ex-Situ Neural Network Transfer onto Passive TiO2 ReRAM Crossbars

Passive resistive random access memory (ReRAM) crossbar arrays, a promising emerging technology used for analog matrix-vector multiplications, are far superior to their active (1T1R) counterparts in terms of the integration density. However, current transfers of neural network weights into the conductance state of the memory devices in the crossbar architecture are accompanied by significant losses in precision due to hardware variabilities such as sneak path currents, biasing scheme effects and conductance tuning imprecision. In this work, training approaches that adapt techniques such as dropout, the reparametrization trick and regularization to TiO2 crossbar variabilities are proposed in order to generate models that are better adapted to their hardware transfers. The viability of this approach is demonstrated by comparing the outputs and precision of the proposed hardware-aware network with those of a regular fully connected network over a few thousand weight transfers using the half moons dataset in a simulation based on experimental data. For the neural network trained using the proposed hardware-aware method, 79.5% of the test set's data points can be classified with an accuracy of 95% or higher, while only 18.5% of the test set's data points can be classified with this accuracy by the regularly trained neural network.Comment: 15 pages, 11 figure

Hybrid cross correlation and line-scan alignment strategy for CMOS chips electron-beam lithography processing

International audienc

Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing

Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a complete CMOS-compatible fabrication process of TiO2-based passive memristor crossbars with 700 nm wide electrodes. We show successful bottom electrode fabrication by a damascene process, resulting in an optimised topography and a surface roughness as low as 1.1 nm. DC sweeps and voltage pulse programming yield statistical results related to synaptic-like multilevel switching. Both cycle-to-cycle and device-to-device variability are investigated. Analogue programming of the conductance using sequences of 200 ns voltage pulses suggest that the fabricated memories have a multilevel capacity of at least 3 bits due to the cycle-to-cycle reproducibility.Comment: 18 pages, 4 figures in main text, 5 figures in S

Analog programming of CMOS-compatible Al2O3/TiO2−x memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming

Exploration of memristors' behavior at cryogenic temperatures has become crucial due to the growing interest in quantum computing and cryogenic electronics. In this context, our study focuses on the characterization at cryogenic temperatures (4.2 K) of TiO2−x-based memristors fabricated with a CMOS-compatible etch-back process. We demonstrate a so-called cryogenic reforming (CR) technique performed at 4.2 K to overcome the well-known metal-insulator transition (MIT), which limits the analog behavior of memristors at low temperatures. This cryogenic reforming process was found to be reproducible and led to a durable suppression of the MIT. This process allowed to reduce by ∼20% the voltages required to perform DC resistive switching at 4.2 K. Additionally, conduction mechanism studies of memristors before and after cryogenic reforming from 4.2 to 300 K revealed different behaviors above 100 K, indicating a potential change in the conductive filament stoichiometry. The reformed devices exhibit a conductance level that is 50 times higher than ambient-formed memristor, and the conduction drop between 300 and 4.2 K is 100 times smaller, indicating the effectiveness of the reforming process. More importantly, CR enables analog programming at 4.2 K with typical read voltages allowing to store up to 4 bits of information on a single CR memristor. Suppressing the MIT improved the analog switching dynamics of the memristor leading to ∼250% larger on/off ratios during long-term depression (LTD)/long-term potentiation (LTP) resistance tuning. This enhancement opens up the possibility of using TiO2−x-based memristors to be used as synapses in neuromorphic computing at cryogenic temperatures

Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing

International audienceBrain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a complete CMOS-compatible fabrication process of TiO2-based passive memristor crossbars with 700 nm wide electrodes. We show successful bottom electrode fabrication by a damascene process, resulting in an optimised topography and a surface roughness as low as 1.1 nm. DC sweeps and voltage pulse programming yield statistical results related to synaptic-like multilevel switching. Both cycle-to-cycle and device-to-device variability are investigated. Analogue programming of the conductance using sequences of 200 ns voltage pulses suggest that the fabricated memories have a multilevel capacity of at least 3 bits due to the cycle-to-cycle reproducibility

Damascene versus subtractive line CMP process for resistive memory crossbars BEOL integration

In recent years, resistive memories have emerged as a pivotal advancement in the realm of electronics, offering numerous advantages in terms of energy efficiency, scalability, and non-volatility [1]. Characterized by their unique resistive switching behavior, these memories are well-suited for a variety of applications, ranging from high-density data storage to neuromorphic computing [2]. Their potential is further enhanced by their compatibility with advanced semiconductor processes, enabling seamless integration into modern electronic circuits [3]. A particularly promising avenue for resistive memory lies in its integration at the Back-End-of-Line (BEOL) stage of semiconductor manufacturing [4]. BEOL integration involves processes that occur after the fabrication of the transistors, primarily focusing on creating interconnections that electrically link these transistors. Integrating resistive memories at this stage can lead to compact, efficient, and high-performance architectures, pivotal for in-memory computing applications where data storage and processing are co-located [5]. This paper studies three ways to integrate TiOx-based resistive memory into passive crossbar array structures, using chemical mechanical polishing (CMP) processes, focusing on identifying the optimal integration techniques

Memristor-based cryogenic programmable DC sources for scalable in-situ quantum-dot control

Current quantum systems based on spin qubits are controlled by classical electronics located outside the cryostat at room temperature. This approach creates a major wiring bottleneck, which is one of the main roadblocks toward truly scalable quantum computers. Thus, we propose a scalable memristor-based programmable DC source that could be used to perform biasing of quantum dots inside of the cryostat (i.e. in-situ). This novel cryogenic approach would enable to control the applied voltage on the electrostatic gates by programming the resistance of the memristors, thus storing in the latter the appropriate conditions to form the quantum dots. In this study, we first demonstrate multilevel resistance programming of a TiO2-based memristors at 4.2 K, an essential feature to achieve voltage tunability of the memristor-based DC source. We then report hardwarebased simulations of the electrical performance of the proposed DC source. A cryogenic TiO2-based memristor model fitted on our experimental data at 4.2 K was used to show a 1 V voltage range and 100 uV in-situ memristor-based DC source. Finally, we simulate the biasing of double quantum dots enabling sub-2 minutes in-situ charge stability diagrams. This demonstration is a first step towards more advanced cryogenic applications for resistive memories such as cryogenic control electronics for quantum computers