Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effectiveness of local back gate to enable switchable ambipolar functionality. Moreover, and, nand, nor, xor, and xnor binary logic functions can be obtained with a single gate, depending on the encoding values used for the input signals. Repeatable behaviors of DIG SiNW FETs are considered as enablers for ambipolar-controlled logic, with all the benefits related to the maturity of the silicon technology

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal–oxide–semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal–oxide–semiconductor (CMOS) cofabrication with a CMOS-compatible process

Ambipolar Si Nanowire Field Effect Transistors for Low Current and Temperature Sensing

This paper reports on the fabrication and characterization of a pA current and temperature sensing device with ultra-low power consumption based on a Schottky barrier silicon nanowire transistor. Thermionic and trap-assisted tunneling current conduction mechanisms are identified and discussed on the base of the device sensitivity upon current and temperature biasing. In particular, very low current sensing properties are confirmed also with previously reported polysilicon- channel nanowire Schottky barrier transistors. demonstrating that these devices are suitable for temperature and current sensing applications. Moreover, the process flow compatibility for both sensing and logic applications makes these devices suitable for heterogeneous integration

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fabrication methodology is demonstrated for curved and straight SiNW arrays with different shapes and levels. Ultra-high density SiNW arrays with round or rhombic cross-sections diameters as low as 10 nm are demonstrated for vertical and horizontal spacing of 60 nm. The uniqueness of the technique, which achieves several advantages such as bulk-Si processing, low-thermal budget, and wide process window makes this fabrication method suitable for a very broad range of applications such as nano-electro-mechanical systems (NEMS), nano-electronics and bio-sensing

Graphene Field Effect Devices Operating in Differential Configuration

After decades of miniaturization and performance tuning, Silicon electronics is approaching its technological limits. In the search for alternative transistor channel materials, Graphene has been given much attention since its discovery in 2004, mainly because it offers compelling values of carrier mobility and a consequent potential for high frequency operation, possibly reaching into the THz range. Certain drawbacks however, such as the weak or absent current saturation or the high “off’ current, limit the use of Graphene for traditional CMOS-like circuitry. Here we investigate the possibility of employing an alternative approach based on differential signaling, where saturation and off-current are not expected to preponderate

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that are distinctly different from those used for CMOS technologies. In this paper, three alternative emerging technologies are showcased in terms of their re- quirements for design implementation and in terms of poten- tial advantages. First, a CMOS evolutionary approach based on vertically-stacked gate-all-around Si nanowire FETs is discussed. Next, an alternative design methodology based on ambipolar carbon nanotube FETs is presented. Finally, a novel approach based on the recently discovered memristive devices is presented, offering the possibility of combining memory and logic functions

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangement of nanowire transistors with near-ideal characteristics, and opens the possibility for design optimization by adjusting the number of nanowire stacks without affecting the footprint area of the device. Several libraries for combinational logic synthesis have been designed and implemented for the synthesis of carry-lookahead adders, using the vertically-stacked nanowire technology. The reduction in silicon active area occupancy of vertically-stacked gates are envisaged of great significance for regular cell mapping, in disruptive future applications based on nanowire transistor arrays

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO2 layers as well as metal gate patterning using stencil lithography, demonstrated for the first time. FinFETs with stenciled Al gates are successfully co-fabricated with polycrystalline silicon Ω-gated devices. Stencil lithography is envisaged as a key enabler for gate patterning on 3D structures, such as vertically stacked nanowire transistors

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching of Pt/TiO2/Pt thin films are first characterized with resistance ratio up to 5 orders of magnitude. Then co-integration of Pt/TiO2/Pt or Pt/TiO2 memory cells on 140 um and 60 um diameter Cu TSV are fabricated. Repeatable non-volatile bipolar switching of the ReRAM cells are demonstrated for different structures

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior