About the correlation between logical identified faulty gates and their layout characteristics

Electronics play a significant role in modern society in various areas of our daily lives. Companies producing embedded nano-electronic systems have responded to the ever-increasing demand for high-performance chips with the development and production of structurally complex design, both in terms of the number of gates they are composed of and how they are arranged on the silicon surface. Especially devices intended for safety-critical fields, such as the Automotive field, require a thorough and precise testing process before they are fielded. This paper proposes a correlation analysis between candidate faulty logical gates as possible sources of a given failure identified during the Manufacturing Test Flow and their layout characteristics on the silicon. It is meaningful feedback for manufacturers about the quality of their applied tests. The experimental results are reported for data regarding a production lot of an Automotive System-on-Chip belonging to the SPC58 family produced by STMicroelectronics

Innovative methods for Burn-In related Stress Metrics Computation

Burn-In equipment provide both external and internal stress to the device under test. External stress, such as thermal stress, is provided by a climatic chamber or by socket-level local temperature forcing tools, and aims at aging the circuit material, while internal stress, such as electrical stress, consists in driving the circuit nodes to produce a high internal activity. To support internal stress, Burn-In test equipment is usually characterized by large memory capabilities required to store precomputed patterns that are then sequenced to the circuit inputs. Because of the increasing complexity and density of the new generations of SoCs, evaluating the effectiveness of the patterns applied to a Device under Test (DUT) through a simulation phase requires long periods of time. Moreover, topology-related considerations are becoming more and more important in modern high-density designs, so a way to include this information into the evaluation has to be devised. In this paper we show a feasible solution to this problem: the idea is to load in the DUT a pattern not by shifting inside of it a bit at a time but loading the entire pattern at once inside of it; this kind of procedure allows for conservative stress measures, thus it fits for stress analysis purposes. Moreover, a method to take the topology of the DUT into account when calculating the activity metrics is proposed, so to obtain stress metrics which can better represent the activity a circuit is subject to. An automotive chip accounting for about 20 million of gates is considered as a case of study. Resorting to it we show both the feasibility and the effectiveness of the proposed methodology

ICS2 - Industry Case-Study Presentations Session 2

Evaluating Burn-In related Metrics for large Automotive Systems-on-Chip. Francesco ANGIONE1, Paolo BERNARDI1, Andrea CALABRESE1, Stefano QUER1, Davide APELLO2, Vincenzo TANCORRE2, Roberto UGIOLI2 1Politecnico di Torino, Italy, 2STMicroelectronics, ItalyMBSA Approaches Applied to Next Decade Digital Components. Tiziano FIORUCCI1, Jean-Marc DAVEAU1, Emmanuel ARBARETIER2, GIORGIO DI NATALE3, Thomas JACQUET2 1STMicroelectronics, Crolles, Frances, 2APSYS-AIRBUS, France, 3Univ. Grenoble Alpes/CNRS/TIMA, FranceMonitoring and controlling handler temperature. Guy DECABOOTER Onsemi, Belgiu

ICS1 - Industry Case-Study Presentations Session 1

Strategies for Enabling Quantum Development with Test and Measurement at millikelvin range focusing on pre-characterization. Jack DEGRAVE1, Philip KRANTZ2, Dong-Thuc KNOBBE1 1FormFactor, USA, 2Keysight, USAChallenges and Solutions for Automotive Cold Test Elimination. Chen HE NXP Semiconductors, USARETE: DfRT, Test for Reliability & Data Analysis for zero defects and zero scraps. Mauro PIPPONZI, Alessandro MASERI, Luca MORICONI ELES Semiconductor Equipment, Italy3D interconnect Test Challenge. Sreejit CHAKRAVARTY Intel, US