Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail

Optimization of the front-end electronics of Drift Tube chambers for high-rate operation

Monitored Drift Tube (MDT) chambers account for the vast majority of precision tracking chambers in the Muon Spectrometer of the ATLAS experiment at the Large Hadron Collider (LHC), where they have to sustain unprecedentedly high background radiation. New, so-called sMDT chambers with reduced tube diameter have been developed for operation at even higher rates, expected after the upgrade of the LHC to high luminosities (HL-LHC). A new ASD chip is required for future upgrades of the MDT chamber front-end electronics and desirable for full exploitation of the rate capability of the sMDT chambers

An 8-Channel ASD in 130 nm CMOS for ATLAS Muon Drift Tube Readout at the HL-LHC

Spatial resolution and efficiency of the ATLAS muon Monitored Drift Tubes (MDT) depend on drift time resolution, noise levels, and accurate threshold setting. A new 130~nm readout device is developed and optimized for the required time resolution, to guarantee rise times below 10~ns with acceptable time slewing effects. Moreover, the large chain-amplification results in increased sensitivity to any disturbance, mainly from the supply. To avoid additional costs to clean up the setup from such disturbances, the readout chain adopts innovative techniques at system, circuit, and design levels. These are minimizing readout chain disturbance sensitivity. This paper describes the achieved performance by showing measurement results and presenting resolution studies taken in a high energy test beam at CERN

Hardware Implementation of a Fast Algorithm for the Reconstruction of Muon Tracks in ATLAS Muon Drift-Tube Chambers for the First-Level Muon Trigger at the HL-LHC

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC where the instantaneous luminosity will exceed the LHC Run 1 instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the resistive plate and thin gap trigger chambers. This limitation can be overcome by including the data of the precision muon drift tube (MDT) chambers in the first level trigger decision. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic. In order to demonstrate the feasibility of reconstructing tracks in MDT chambers within the short available first-level trigger latency of about 3~$\mu$s we implemented a seeded Hough transform on the ARM Cortex A9 microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beam data recorded in CERN's Gamma Irradiation Facility. We could show that by using the ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4 floating point operations in parallel the challenging latency requirement can be matched.The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC where the instantaneous luminosity will exceed the LHC Run 1 instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the resistive plate and thin gap trigger chambers. This limitation can be overcome by including the data of the precision muon drift tube (MDT) chambers in the first level trigger decision. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic. In order to demonstrate the feasibility of reconstructing tracks in MDT chambers within the short available first-level trigger latency of about 3 μs we implemented a seeded Hough transform on the ARM Cortex A9 microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beam data recorded in CERN's Gamma Irradiation Facility. We could show that by using the ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4 floating point operations in parallel the challenging latency requirement can be matched