3D seismic imaging through reverse-time migration on homogeneous and heterogeneous multi-core processors

Abstract. Reverse-Time Migration (RTM) is a state-of-the-art technique in seismic acoustic imaging, because of the quality and integrity of the images it provides. Oil and gas companies trust RTM with crucial decisions on multi-million-dollar drilling investments. But RTM requires vastly more computational power than its predecessor techniques, and this has somewhat hindered its practical success. On the other hand, despite multi-core architectures promise to deliver unprecedented computational power, little attention has been devoted to mapping efficiently RTM to multi-cores. In this paper, we present a mapping of the RTM computational kernel to the IBM Cell/B.E. processor that reaches close-tooptimal performance. The kernel proves to be memory-bound and it achieves a 98% utilization of the peak memory bandwidth. Our Cell/B.E. implementation outperforms a traditional processor (PowerPC 970MP) in terms of performance (with an 15.0× speedup) and energy-efficiency (with a 10.0× increase in the GFlops/W delivered). Also, it is the fastest RTM implementation available to the best of our knowledge. These results increase the practical usability of RTM. Also, the RTM-Cell/B.E. combination proves to be a strong competitor in the seismic arena

Abstract A Parsing Technique for Tile Rewriting Picture Grammars

Recently, a novel model, called Tile Rewriting Grammar (TRG), has been introduced to apply the generative grammar approach to picture languages, or 2D languages. In many respects, the TRGs can be considered the equivalent of context-free (CF) grammars for 2D languages. However, the possibility to investigate applications was precluded so far by the lack of a good parsing algorithm. We propose a parsing algorithm for TRGs, which can be described as an extension to 2D of Cocke, Kasami and Younger’s classical parsing technique for 1D context-free grammars.

Early Estimation of the Size of VHDL Projects

The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimation of the effort involved in a development process is a key requirement for any cost-driven system-level design decision. In this paper, we present a methodology to predict the final size of a VHDL project on the basis of a high-level description, obtaining a significant indication about the development effort. The methodology is the composition of a number of specialized models, tailored to estimate the size of specific component types. Models were trained and tested on two disjoint and large sets of real VHDL projects. Quality-of-result indicators show that the methodology is both accurate and robust