A novel framework for the design of adaptable reconfigurable partitions for the placement of variable-sized ip cores

International audienceThis letter presents a novel framework for the design of adjustable reconfigurable partitions for the placement of variable- sized IP cores on embedded reconfigurable systems. It enables the rapid and easy to use methodology for the generation of adaptive computation and communication infrastructure for partial dynamic reconfiguration. The methodology allows an adaptable partition and efficient resource utilization for the placement of reconfigurable modules. The different steps of the proposed framework are detailed. Its effectiveness and benefits are demonstrated through the use of a practical example implemented on a tiled reconfigurable architecture

An embedded system for AC series arc detection by inter-period correlations of current

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