The high-mobility bended n-channel silicon nanowire transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices

Beyond Scaling:Physics and Modeling for Pushing the Frontiers of Low-Power Devices

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leading to an impending power crisis in which static power consumption reaches unacceptably high levels. Indeed, due to the relation between supply voltage (VD D ) and power dissipation of modern circuit technologies, when the supply voltage has been reduced from 0.5V to 0.25V while preserving the same overdrive, the leakage power in a 45-nm bulk CMOS technology has been shown to increase by a factor 275 . The work in this thesis proposes two synergic, promising strategies to overcome such limitations. The first aims to accompany conventional CMOS devices toward their ultimate limits of miniaturization via the Gate-All-Around (GAA) architecture, while the second relies on a new emerging device, the Tunnel-FET, which is based on a different working principle that anticipates remarkable advantages in the context of low-supply voltage applications. In particular, these two solutions allow three different scenarios. The GAA is able to provide the same Ion of High Performance (HP) planar MOSFET with a remarkable Ioff reduction thanks to a subthreshold swing improvement down to ∼ 60mV/dec at room temperature, with respect to ∼ 100mV/dec and ∼ 120mV/dec of planar Si-FETs and III-V FETs respectively. Whereas in the context of moderate performance or subthreshold region operation, when compared to CMOS, Tunnel-FETs offer superior performance at same low-supply voltage (for VDD < 0.4V ), or significant power reduction at same performance (because of a VDD reduction enabled by the steep off-on transition). Via the presentation of basic electrostatic concepts of heteromaterial systems common to both MOSFET and Tunnel-FETs and the Short-Channel-Effects that are plaguing planar CMOS of the current generation, we show that the Gate-All-Around device proves to be a pivotal solution capable of addressing the limitations of the aforementioned currently-used transistors. In particular, we study peculiarities of multi-gate devices with polygonal cross sections (such as those fabricated in our lab), namely corner effects and local volume inversion, and propose a model for the device electrostatics by means of an approximate solution to the 3D Poisson’s equation. We then provide the setting for our second research contribution by introducing the interband tunneling. A Band-to-Band Tunneling (BTBT) model is implemented in a full-band Monte Carlo simulator, the results of which are presented and analyzed. An analytical compact model for reverse-biased diodes is also developed and implemented in Verilog-A SPICE circuit simulator. We show that this model, validated by means of finite element simulations and comparison with experimental data, successfully describes and models both direct and indirect BTBT in both homo- and hetero-junction devices. Our final research contribution provides a launch pad for future research via an in-depth study and analysis of the conventional Tunnel-FET: device electrostatics, charge carriers and Fermi-Dirac distribution dependence on terminal biases are related to device-current dependence and peculiar features of such transistors, such as poor driving capability of all-Silicon devices, superlinear onset of output characteristics and progressively-degraded subthreshold swing by increased source doping, are explained. We develop and propose improved device architectures that prove to be extremely promising with superior potential towards the end of vastly improved performance within the low supply voltage domain. We further provide a DC analytical model and we performe circuit analyses to project and extrapolate the potential performance of Tunnel-FET, with the objective of predicting the spectrum of applications where it proves to be superior than conventional CMOS

A model for robust electrostatic design of nanowire FETs with arbitrary polygonal cross sections

In this work a quasi-analytical physical model for the accurate prediction of the potential of GAA nanowire transistors with an arbitrary regular polygon as a cross section is developed. Two case studies concerning triangular and square cross-sections are particularly investigated and analyzed. The model is then extended to the transport direction; general expressions for the natural length are derived and validated by means of two- and three-dimensional numerical device simulations. Basic design guidelines, using an original analytical expression of the natural length, for robust electrostatic design are proposed, to predict the minimum technological gate length able to assure immunity to the SCEs

A model for robust electrostatic design of nanowire FETs with arbitrary polygonal cross sections

In this work a quasi-analytical physical model for the accurate prediction of the potential of GAA nanowire transistors with an arbitrary regular polygon as a cross section is developed. Two case studies concerning triangular and square cross-sections are particularly investigated and analyzed. The model is then extended to the transport direction; general expressions for the natural length are derived and validated by means of two- and three-dimensional numerical device simulations. Basic design guidelines, using an original analytical expression of the natural length, for robust electrostatic design are proposed, to predict the minimum technological gate length able to assure immunity to the SCEs

A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section

In this work a quasi-analytical physical model has been developed for the prediction of the potential in SiNW devices with arbitrary polygonal cross section. The model is then extended to the transport direction; a method for the calculation of the natural channel length has been proposed and validated by means of 2D and 3D numerical device simulations. With the results based on the proposed model it is possible to compare nanowires with cross sections of different shape and predict the minimum technological gate length able to assure immunity to the SCEs

The electron–hole bilayer tunnel FET

We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSavg ∼ 10 mV/dec over 7 decades of current) and Ion/Ioff > 10^8 at Vd = Vg = 0.5 V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the Ion (∼11 μA/μm at Vdd = 0.5 V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs

Corner Effect and Local Volume Inversion in SiNW FETs

In this paper, a quantitative study of the corner effect and of the local volume inversion on gate-all-around MOSFETs based on numerical simulations has been carried out; different angles and doping levels are compared, in order to understand the impact of the corner regions on the total current. A method for the extraction of the threshold voltage and of the subthreshold slope of the corner region has been proposed, and the resulting values have been analyzed in order to understand their effects on the device characteristics.NANOLA

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

5The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications . Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA). Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. In conclusion with this work we have shown that although commonly fabricated TFETs feature source/channel interfaces normal to the transport direction, in a well-designed TFET the tunneling junction should have the same orientation of the component of the electric field modulated by the gate: only in this case the gate can effectively modulate the tunneling barrier, resulting in a steeper average SS and higher ION.reservedmixedDe Michielis L; Lattanzio L; Palestri P; Selmi L; Ionescu A. M.DE MICHIELIS, Luca; Lattanzio, L; Palestri, Pierpaolo; Selmi, Luca; Ionescu, A. M

Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current

We propose a novel Tunnel field-effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron-hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p-i-n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Near ideal average subthreshold slope (SSavg ~ 12 mV/dec over 6 decades of current) and Ion/Ioff >; 10^8 at Vd = Vg = 0.5 V figures of merit are obtained, due to the OFF-ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the silicon channel. Drive current (Ion) in the EHBTFET is 3× higher that in traditional all-Si Tunnel FET but below 0.1 μA/μm

Complementary Germanium Electron-Hole Bilayer Tunnel FET for Sub-0.5-V Operation

In this paper we present a novel device, the Germanium Electron-Hole Bilayer Tunnel FET (Ge EHBTFET), which exploits carrier tunneling through a bias-induced electron-hole bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2D numerical simulations. This device allows interesting features in terms of low operating voltage (< 0.5 V), due to its super-steep subthreshold slope (SSavg ~ 13 mV/dec over 6 decades of current), Ion/Ioff ratio of 10^9, and drive current Ion ~ 10 uA/um at Vdd = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with Ion and Ioff levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when Vdd = 0.25 V