Transformation-Based Verification Using Generalized Retiming

In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based design representation without changing its actual input-output behavior. We discuss the application of retiming to minimize the number of registers with the goal of increasing the capacity of symbolic state traversal. In particular, we demonstrate that the classical definition of retiming can be generalized for verification by relaxing the notion of design equivalence and physical implementability. This includes (1) omitting the need for equivalent reset states by using an initialization stump, (2) supporting negative registers, handled by a general functional relation to future time frames, and (3) eliminating peripheral registers by converting them into simple temporal offsets. The presented results demonstrate that the application of retiming in verification can significantly increase the capacity of symbolic state traversal. Our experiments also demonstrate that the repeated use of retiming interleaved with other structural simplifications can yield reductions beyond those possible with single applications of the individual approaches. This result suggests that a tool architecture based on re-entrant transformation engines can potentially decompose and solve verification problems that otherwise would be infeasible

Combined approach of ROBDDs and structural analysis in the mapping and matching of logic functions

The technology mapping - final step of the logic synthesis - maps the decomposed Boolean function on physical cells. We address here the decomposition and the matching steps. We present two different ROBDD-based techniques to handle the decomposition problem, and compare them. For handling the matching step, we analyse a heuristics based on symmetry and develop a new structural approach, based on controlling value analysis and observation function deduction. This last appears to be efficient regarding the CPU time for checking the match with basic cells, mostly when don't cares are present, and should be particularly interesting to handle the complex cells of FPGAs. Benchmarks are presented which validate the various heuristics. Keywords ROBDD, technology mapping, decomposition, matching 1 INTRODUCTION Technology mapping is the last and decisive step in logic synthesis. It is usually performed after a technology independent minimization, which generates an optimized multi-level logic..