227 research outputs found

    CMOS Compatible Anodic Al2O3 Based Sensors for Bacteria Detection

    Get PDF
    AbstractRapid, real-time detection of pathogenic microorganisms is an emerging evolving field of research, especially for microorganisms that pose a major threat to public health. Alumina covered interdigitated capacitive microsensors were previously designed in our laboratory for DNA hybridization electrical detection (LOD of 30 nM target DNA). The device is constructed with standard CMOS materials. We show here that when coated with an appropriate anti- Staphylococcus aureus monoclonal antibody (MoAb), this device also permits to specifically detect this bacteria. The binding of bacteria to the microsensors induce a significant capacitance shift that is proportional to the amount of immobilized bacteria, thus enabling a possible quantitative analysis

    An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications

    No full text
    An accumulation mode SOI pMOSFET model for simulation of analog circuits meant for high-temperature applications is presented in the paper. The model is based on explicit expressions for the drain current with an infinite order of continuity what assures smooth transitions between different operation regimes of the transistor. This model is valid for all regimes of normal operation, demonstrates proper description of high-temperature behavior of the subthreshold and off-state current. The model characteristics show a good agreement with the experimental data for temperatures up to 300 °C

    High-Temperature Stable Operation of Nanoribbon Field-Effect Transistors

    Get PDF
    We experimentally demonstrated that nanoribbon field-effect transistors can be used for stable high-temperature applications. The on-current level of the nanoribbon FETs decreases at elevated temperatures due to the degradation of the electron mobility. We propose two methods of compensating for the variation of the current level with the temperature in the range of 25–150°C, involving the application of a suitable (1) positive or (2) negative substrate bias. These two methods were compared by two-dimensional numerical simulations. Although both approaches show constant on-state current saturation characteristics over the proposed temperature range, the latter shows an improvement in the off-state control of up to five orders of magnitude (−5.2 × 10−6)

    Characterization of charge trapping processes in fully-depleted UNIBOND SOI MOSFET subjected to γ-irradiation

    No full text
    An investigation of radiation effect on edgeless accumulation mode (AM) p-channel and fully-depleted enhancement mode (EM) n-channel MOSFETs, fabricated on UNIBOND silicon on insulatior wafers (SOI), is presented in the paper. Characterization of trapped charge in the gate and buried oxides of the devices was performed by measuring only the front-gate transistors. It was revealed that the irradiation effect on EM n-MOSFET is stronger than that on AM p-MOSFET. Radiation-induced positive charge in the buried oxide proved to invert back interface what causes back channel creation in EM n-MOSFET but no such effect in AM p-MOSFET has been not observed. The effect of improving the quality of both interfaces for small irradiation doses is demonstrated

    Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs

    No full text
    The charge coupling between the gate and substrate is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOS transistor, which manifests itself as a dependence of electrical characteristics at one Si film/dielectric interface on charges at the opposite interface and opposite gate bias. Traditionally, gate-to-substrate coupling in SOI MOS transistors is described by the classical Lim-Fossum model. However, in the case of SOI MOS transistors with ultra-thin silicon bodies, significant deviations from this model are observed. In this paper, the behavior of gate coupling in SOI MOS structures with ultra-thin silicon films and ultra-thin gate dielectrics is studied and analyzed using experimental data and one-dimensional numerical simulations in classical and quantum-mechanical modes. It is shown that in these advanced transistor structures, coupling characteristics (dependences of the front- and back-gate threshold voltages on the opposite gate bias) feature a larger slope and much wider (more than doubled) linear region than that predicted by the Lim-Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects and being in good agreement with numerical simulations and experimental results is proposed

    Low-Power Dihexylquaterthiophene-Based Thin Film Transistors for Analog Applications

    Get PDF
    peer reviewedWe have optimized dihexylquaterthiophene-based thin film transistors for low-power consumption and have studied their characteristics for potential introduction in analog circuits. Bottom-gate devices with Pd source and drain electrodes have been fabricated by employing different gate dielectrics. Transistors with very thin («10 nm) silicon oxynitride dielectrics display subthreshold swing values below 100 mV/decade, cutoff frequencies approaching the kilohertz range and intrinsic gain around 45 dB, suggesting that they are promising candidates for low-power analog integration
    corecore