Time-resolved temperature measurements during pulsed laser irradiation uslng thin film metal thermometers

In this article, we describe a technique using Nisi and Pt thin film metal thermometers to provide accurate temperature information on a nanosecond time scale during pulsed laser processing of materials. A surface layer of interest is deposited onto the thermometer layer, and temperatures are determined from temperature dependent changes in the metal film's resistance. Details concerning the design and fabrication of the device structure and experimental considerations in making nanosecond resolved resistance measurements are discussed. Simple analytical estimates are presented to extract quantities such as incident laser energy stored in the sample. Finally, transient temperature data in the thermometer film, in combination with heat flow calculations, allow temperature determination as a function of time and depth into the sample and, additionally, can provide information about material properties of the surface layer

Energy and spatial distribution of traps in SiO2/Al 2O3 nMOSFETs

The energy and spatial profiling of the interface and near-interface traps in n-channel MOSFETs with SiO2/Al2O3 gate dielectrics is investigated by charge-pumping (CP) measurements. By increasing the amplitude as well as lowering the frequency of the gate pulse, an increase of the charge recombined per cycle was observed, and it was explained by the contributions of additional traps located higher in energy and deeper in position at the SiO2/Al2O3 interface. In addition, CP currents, acquired after different constant voltage stress, have been used to investigate the trap generation in this dielectric stack. © 2006 IEEE

Distribution and generation of traps in SiO2/Al2O3 gate stacks

In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO2/Al2O3 n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO2 interface. © 2007 Elsevier Ltd. All rights reserved

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

In this paper, a comprehensive study of hot-carrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement