Providing a computing environment for a high energy physics workshop

Although computing facilities have been provided at conferences and workshops remote from the host institution for some years, the equipment provided has rarely been capable of providing for much more than simple editing and electronic mail. This report documents the effort involved in providing a local computing facility with world-wide networking capability for a physics workshop so that we and others can benefit from the knowledge gained through the experience

NULLJOB product

The ever increasing demand for more CPU cycles for data analysis on our Central VAX Cluster led us to investigate new ways to utilize more fully the resources that were available. A review of the experiment and software development VAX systems on site revealed many unused computing cycles. Furthermore, these systems were all connected by DECnet which would allow easy file transfer and remote batch job submission. A product was developed to allow jobs to be submitted on the Central VAX Cluster but actually to be run on one of the remote systems. The processing of the jobs was arranged, to the greatest extent possible, to be transparent to the user and to have minimal impact on both the Central VAX Cluster and remote systems

Progress in SiC MOSFET Reliability

In this work, we have characterized a variety of SiC devices (first- and second-generation 1200 V SiC MOSFETs and 1200 V SiC JFETs) with regards to threshold voltage shifts and leakage currents at high temperatures under both static and dynamic gate bias stress conditions. It was found that, although the stability of SiC MOSFETs has increased dramatically from the first- to the second-generation due to an increase in the quality of the gate oxide layer, SiC JFET devices (which lack a gate oxide altogether) are much more stable with respect to ΔVT for both types of gate bias stresses at high temperatures. We have also characterized the interface trap density (DIT) in SiC MOSFETs based solely on changes in the sub-threshold slope of the devices’ I-V curves under elevated temperature and bias stress, and have produced ∆DIT profiles showing relative changes in interfacial defect concentration at energy levels referenced to the calculated surface potential at the threshold voltage. We have found that the defect density of second-generation SiC MOSFETs is almost an order of magnitude lower than similar first-generation devices from the same manufacturer, consistent with the decreased VT shifts seen in voltage/temperature stress experiments.</jats:p

Characterization of Reliability in SiC Power Devices

The low intrinsic carrier concentrations, high breakdown voltages, and high thermal conductivities of wide-bandgap semiconductors make them attractive alternatives to traditional Si-based power electronics, especially for high-temperature/power switching applications such as motor drives, hybrid electric vehicles, and photovoltaic inverters. Silicon Carbide (SiC) is an especially strong candidate to replace Si devices due to widespread availability of SiC substrates, vertical device topologies, and the ability to thermally grow a silicon dioxide (SiO2) layer on SiC to serve as a gate dielectric, similar to established Si technology. SiC MOSFETs have been commercially available for over three years with blocking voltage of 1200V and excellent on-state resistances (~80 mΩ). In addition, SiC MOSFETs may be able to operate at higher temperatures than competing Si IGBTs or MOSFETs. Currently the most significant hurdles to market penetration are reliability and cost. SiC MOSFET reliability challenges stem mainly from poor SiC/SiO2 interface quality. When operated under high gate field and temperatures, threshold voltage (VT) instabilities are often observed both in SiC MOSFET [1] and MOS capacitor [2] structures, primarily due to the large number of electrically active SiO2 bulk and SiC/SiO2 interface states [3]. The application of a gate voltage (VG) may result in electron (positive VG) or hole (negative VG) injection from the SiC into the oxide, populating traps at the SiO2/SiC interface and/or within the SiO2 bulk. These populated traps alter the surface potential and shift the VT necessary to switch the device. Recent measurements on second-generation commercially available SiC MOSFETs indicate significant progress on this front compared to earlier devices, although appreciable VTshifts still exist for relatively moderate stresses (Fig. 1a). We have characterized 1200 V SiC MOSFETs as well as Junction FETs (JFETs), which do not utilize a gate oxide, at high temperatures under both static and dynamic gate bias stress conditions. SiC JFET devices demonstrate more stable VT than SiC MOSFET devices for both types of gate bias stresses at high temperatures (Fig. 1b). For static gate bias stresses, packaged JFET devices exhibited a negligible VT shift (ΔVT &lt; 2 mV) for temperatures up to 250oC. At higher temperatures, bare JFET die demonstrated ΔVT &lt; 10 mV up to 525oC. Further, in contrast to the SiC MOSFETs, the VTof the SiC JFETs was unaffected by dynamic gate bias stress over the test period, although the sub-threshold leakage current increased with time [4]. In addition to monitoring VT shifts, we have calculated the change in density of SiC/SiO2 interface traps (ΔDIT) due to the application of gate stress to MOSFETs. These profiles can be extracted from I-V curves for SiC MOSFETs based on the changes in sub-threshold slope. This technique can either be used to determine ΔDIT (if body doping and gate capacitance are unknown) or absolute DIT at specific energies within the bandgap (if doping and capacitance are known) [5]. This work was performed under the DOE Office of Electricity programs managed by Dr. Imre Gyuk. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000. [1] A. J. Lelis, et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," IEEE Trans. Electr. Dev., vol. 55 (8), pp. 1835-1840, 2008. [2] M. J. Marinella, et al., "Evidence of Negative Bias Temperature Instability in 4H-SiC Metal Oxide Semiconductor Capacitors," Appl. Phys. Lett., vol. 90 (25), pp. 253508-253508, 2007. [3] D. K. Schroder, "Progress In SiC Materials/Devices and Their Competition," Int. J. High Speed Electr. and Syst., vol. 21 (1), p. 1250009, Apr 2012. [4] J. Flicker, et al., "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures," High Temperature Electronics Conference (HiTEC), Albuquerque, NM, 2014. [5] D. R. Hughart, et al., "Sensitivity Analysis of a New Technique for Trapped Charge Extraction in SiC MOSFETs from Subthreshold Characteristics " International Reliability Physics Symposium (IRPS), Waikoloa, HI, 2014. </jats:p