Post-assembly modification of kinetically metastable Fe(II)2L3 triple helicates.

We report the covalent post-assembly modification of kinetically metastable amine-bearing Fe(II)2L3 triple helicates via acylation and azidation. Covalent modification of the metastable helicates prevented their reorganization to the thermodynamically favored Fe(II)4L4 tetrahedral cages, thus trapping the system at the non-equilibrium helicate structure. This functionalization strategy also conveniently provides access to a higher-order tris(porphyrinatoruthenium)-helicate complex that would be difficult to prepare by de novo ligand synthesis.This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC). D.A.R. acknowledges the Gates Cambridge Trust for Ph.D. (Gates Cambridge Scholarship) and conference funding.This is the final published version. It first appeared at http://pubs.acs.org/doi/abs/10.1021/ja5042397

A UML Model-Driven Approach to Efficiently Allocate Complex Communication Schemes

International audience<p>To increase the performance of embedded devices, the cur- rent trend is to shift from serial to parallel and distributed computing with simultaneous instructions execution. The performance increase of parallel computing wouldn’t be possible without efficient transfers of data and control information via complex communication architectures. In UML/SysML/MARTE, different solutions exist to describe and map computations onto parallel and distributed systems. However, these lan- guages lack expressiveness to clearly separate computation models from communication ones, thus strongly impacting models’ portability, espe- cially when performing Design Space Exploration. As a solution to this issue, we present Communication Patterns, a novel UML modeling arti- fact and model-driven approach to assist system engineers in efficiently modeling and mapping communications for parallel and distributed sys- tem architectures. We illustrate the effectiveness of our approach with the design of a parallel signal processing algorithm mapped to a multi- processor platform with a hierarchical bus-based interconnect.</p