Symmetric bifurcation analysis of synchronous states of time-delayed coupled Phase-Locked Loop oscillators

In recent years there has been an increasing interest in studying time-delayed coupled networks of oscillators since these occur in many real life applications. In many cases symmetry patterns can emerge in these networks, as a consequence a part of the system might repeat itself, and properties of this subsystem are representative of the dynamics on the whole phase space. In this paper an analysis of the second order N-node time-delay fully connected network is presented which is based on previous work by Correa and Piqueira \cite{Correa2013} for a 2-node network. This study is carried out using symmetry groups. We show the existence of multiple eigenvalues forced by symmetry, as well as the existence of Hopf bifurcations. Three different models are used to analyze the network dynamics, namely, the full-phase, the phase, and the phase-difference model. We determine a finite set of frequencies $\omega$, that might correspond to Hopf bifurcations in each case for critical values of the delay. The $S_n$ map is used to actually find Hopf bifurcations along with numerical calculations using the Lambert W function. Numerical simulations are used in order to confirm the analytical results. Although we restrict attention to second order nodes, the results could be extended to higher order networks provided the time-delay in the connections between nodes remains equal.Comment: 41 pages, 18 figure

Thirty-eight-year follow-up of the first patient of mandibular reconstruction with free vascularized fibula flap

Background: The mandible is responsible for vital functions of the stomatognathic system, and its loss results in functional and aesthetic impairment. Mandibular reconstruction with free fibula flap is considered the gold standard for mandibular reconstruction. Case presentation: We describe here the 38-year follow-up of the patient who was the first case of mandibular reconstruction with free fibula flap reported in the literature. The original report describes a 27-year-old woman who had undergone extensive mandibulectomy due to an osteosarcoma. A microvascularized fibula flap was used for mandibular reconstruction in 1983. Two years later, a vestibulo-lingual sulcoplasty with skin graft was performed to allow the construction of a total dental prosthesis. Fifteen years after the initial treatment, an autologous iliac crest graft was placed in the fibula flap, aimed at increasing bone thickness and height for rehabilitation with implant supported prosthesis. In 2015, a rib graft was positioned in the mental region, enhancing the support to the soft tissues of the face and improving the oral function. A recent review of the patient shows well-balanced facial morphology and optimal functional results of the procedure. Conclusions: The fibula flap method, described in 1975 and first reported for mandibular reconstruction in 1985, continues to be applied as originally described, especially where soft tissue damage is not extensive. Its use in reconstructive surgery was expanded by advancements in surgery and techniques such as virtual surgical planning. However, there is still a lack of evidence related to the long-term evaluation of outcomes. The present work represents the longest-term follow-up of a patient undergoing mandibular reconstruction with free vascularized fibula flap, presenting results showing that, even after 38 years, the procedure continues to provide excellent results

Long-term behavior of dynamic equilibria in fluid queuing networks

A fluid queuing network constitutes one of the simplest models in which to study flow dynamics over a network. In this model we have a single source-sink pair, and each link has a per-time-unit capacity and a transit time. A dynamic equilibrium (or equilibrium flow over time) is a flow pattern over time such that no flow particle has incentives to unilaterally change its path. Although the model has been around for almost 50 years, only recently results regarding existence and characterization of equilibria have been obtained. In particular, the long-term behavior remains poorly understood. Our main result in this paper is to show that, under a natural (and obviously necessary) condition on the queuing capacity, a dynamic equilibrium reaches a steady state (after which queue lengths remain constant) in finite time. Previously, it was not even known that queue lengths would remain bounded. The proof is based on the analysis of a rather nonobvious potential function that turns out to be monotone along the evolution of the equilibrium. Furthermore, we show that the steady state is characterized as an optimal solution of a certain linear program. When this program has a unique solution, which occurs generically, the long-term behavior is completely predictable. On the contrary, if the linear program has multiple solutions, the steady state is more difficult to identify as it depends on the whole temporal evolution of the equilibrium

Estudio socioeconómico sobre la zona de Córdoba en el Municipio De Ciénaga Departamento Del Magdalena.

El presente trabajo se realizó en la zona de Córdoba, Municipio de Ciénaga, Departamento del Magdalena, en el año de 1975. La zona estudiada presenta las siguientes características generales: Topografía plana, clima cálido, con temperatura pro - medio de 30.4°C; la zona estudiada cuenta con numerosas vías de comunicación y además se encuentra situada entre Ciénaga y Santa Marta, grandes centros consumidores. El cuestionario utilizado fue elaborado con la asesoría del Presidente del trabajo y teniendo como base, formularios obtenidos de otros trabajos socio-económicos. Para el efecto se hicieron 71 encuestas a respectivamente 71 jefes de familias escogidos al. azar, dentro del número total de - familias de la población. En las características generales de la zona de Córdoba, se estudiaron datos esenciales como: Aspectos geográficos, hidrológicos, históricos, climáticos, antropológicos, lo mismo que la fauna y flora. A continuación, se analiza la demografía y los aspectos sociales, tales como población, la familia, la educación, migración, la vivienda, la alimentación, la salud e higiene, las actitudes y creencias, las recreaciones y diversiones, liderazgo, grupos sociales, problemas comunitarios y por último la ocupación o el empleo. De los resultados obtenidos se puede decir que solo el 18.32 % de la población encuestada son propietarios de tierra; el estado educacional no es satisfactorio, ya que sólo se cursa regularmente hasta el cuarto ario de primaria. La población en general carece de servicios tales como: acueducto rural, centro de salud, mejoras de escuelas, farmacia comunal, puesto de vigilancia policivo, además de servicio urbano de buses, red eléctrica, parques y otros servicios necesarios y de vital importancia para el desarrollo de la comunidad. Seguidamente se hace el análisis de la tenencia de la tierra, tamaño de la propiedad, cultivos predominantes, métodos de preparación del suelo e implementos con que se efectúan las labores en el campo. Después se estudia la explotación ganadera y la distribución de ésta, de acuerdo al número de vacunos, caballos, porcinos, aves etc. Que se censaron. También se detallan los factores económicos. Tales como: los ingresos, el comercio y los intermediarios, el mercado, considerando dentro de éste a las vías de comunicación, el transporte y los sistemas de ventas. Dentro del aspecto del crédito, se analiza el escaso uso que hacen de él las familias encuestadas. Finalmente se expresan recomendaciones que de acuerdo al criterio de los autores podrán ayudar a solucionar los problemas de la comunidad estudiada

Implementation of Ultra-Low Latency and High-Speed Communication Channels for an FPGA-Based HPC Cluster

RÉSUMÉ Les clusters basés sur les FPGA bénéficient de leur flexibilité et de leurs performances en termes de puissance de calcul et de faible consommation. Et puisque la consommation de puissance devient un élément de plus en plus importants sur le marché des superordinateurs, le domaine d’exploration multi-FPGA devient chaque année plus populaire. Les performances des ordinateurs n’ont jamais cessé d’augmenter mais la latence des réseaux d’interconnexion n’a pas suivi leur taux d’amélioration. Dans le but d’augmenter le niveau d’abstraction et les fonctionnalités des interconnexions, la complexité des piles de communication atteinte à nos jours engendre des coûts et affecte la latence des communications, ce qui rend ces piles de communication très souvent inefficaces, voire inutiles. Les protocoles de communication commerciaux existants et les contrôleurs d’interfaces réseau FPGA-FPGA n’ont la performance pour supporter ni les applications à temps critique ni un partitionnement étroitement couplé des systèmes sur puce. Au lieu de cela, les approches de communication personnalisées sont souvent préférées. Dans ce travail, nous proposons une implémentation de canaux de communication à haut débit et à faible latence pour une grappe de FPGA. Le système est constitué de deux BEE3, chacun contenant 4 FPGA de la famille Virtex-5 interconnectés par une topologie en anneau. Notre approche exploite la technologie à transducteur à plusieurs gigabits par seconde pour l’obtention d’une bande passante fiable de 8Gbps. Le module de propriété intellectuelle (IP) de communication proposé permet le transfert de données entre des milliers de coprocesseurs sur le réseau, grâce à l’implémentation d’un réseau direct avec capacité de routage de paquets. Les résultats expérimentaux ont montré une latence de seulement 34 cycles d’horloge entre deux noeuds voisins, ce qui est un des plus bas parmi ceux rapportés dans la littérature. En outre, nous proposons une architecture adaptée au calcul à haute performance qui comporte un traitement extensible, parallèle et distribué. Pour une plateforme à 8 FPGA, l’architecture fournit 35.6Go/s de bande passante effective pour la mémoire externe, une bande passante globale de réseau de 128Gbps et une puissance de calcul de 8.9GFLOPS. Un solveur matrice-vecteur de grande taille est partitionné et mis en oeuvre à travers le cluster. Nous avons obtenu une performance et une efficacité de calcul concurrentielles grâce à la faible empreinte du protocole de communication entre les éléments de traitement distribués. Ce travail contribue à soutenir de nouvelles recherches dans le domaine du calcul parallèle intensif et permet le partitionnement de système sur puce à grande taille sur des clusters à base de FPGA.----------ABSTRACT An FPGA-based cluster profits from the flexibility and the performance potential FPGA technology provides. Since price and power consumption are becoming increasingly important elements in the High-Performance Computing market, the multi-FPGA exploration field is getting more popular each year. Network latency has failed to keep up with other improvements in computer performance. Complex communication stacks have sacrificed latency and increased overhead to achieve other goals, being in most of the time inefficient and unnecessary. The existing commercial offthe- shelf communication protocols and Network Interfaces Controllers for FPGA-to-FPGA interconnection lack of performance to support time-critical applications and tightly coupled System-on-Chip partitioning. Instead, custom communication approaches are preferred. In this work, ultra-low latency and high-speed communication channels for an FPGA-based cluster are presented. Two BEE3s grouping 8 FPGAs Virtex-5 interconnected in a ring topology, compose the targeting platform. Our approach exploits Multi-Gigabit Transceiver technology to achieve reliable 8Gbps channel bandwidth. The proposed communication IP supports data transfer from coprocessors over the network, by means of a direct network implementation with hop-by-hop packet routing capability. Experimental results showed a latency of only 34 clock cycles between two neighboring nodes, being one of the lowest in the literature. In addition, it is proposed an architecture suitable for High-Performance Computing which includes performing scalable, parallel, and distributed processing. For an 8 FPGAs platform, the architecture provides 35.6GB/s off-chip memory throughput, 128Gbps network aggregate bandwidth, and 8.9GFLOPS computing power. A large and dense matrix-vector solver is partitioned and implemented across the cluster. We achieved competitive performance and computational efficiency as a result of the low communication overhead among the distributed processing elements. This work contributes to support new researches on the intense parallel computing fields, and enables large System-on-Chip partitioning and scaling on FPGA-based clusters