Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication

Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping

Room Temperature Lattice Thermal Conductivity of GeSn Alloys

CMOS-compatible materials for efficient energy harvesters at temperatures characteristic for on-chip operation and body temperature are the key ingredients for sustainable green computing and ultralow power Internet of Things applications. In this context, the lattice thermal conductivity (κ) of new group IV semiconductors, namely Ge1–xSnx alloys, are investigated. Layers featuring Sn contents up to 14 at.% are epitaxially grown by state-of-the-art chemical-vapor deposition on Ge buffered Si wafers. An abrupt decrease of the lattice thermal conductivity (κ) from 55 W/(m·K) for Ge to 4 W/(m·K) for Ge0.88Sn0.12 alloys is measured electrically by the differential 3ω-method. The thermal conductivity was verified to be independent of the layer thickness for strained relaxed alloys and confirms the Sn dependence observed by optical methods previously. The experimental κ values in conjunction with numerical estimations of the charge transport properties, able to capture the complex physics of this quasi-direct bandgap material system, are used to evaluate the thermoelectric figure of merit ZT for n- and p-type GeSn epitaxial layers. The results highlight the high potential of single-crystal GeSn alloys to achieve similar energy harvest capability as already present in SiGe alloys but in the 20 °C–100 °C temperature range where Si-compatible semiconductors are not available. This opens the possibility of monolithically integrated thermoelectric on the CMOS platform