Advances, Challenges and Opportunities in 3D CMOS Sequential Integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications

Copper Direct Bonding: an innovative 3D interconnect

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Direct Bonding of Silicon to Platinum

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Epitaxial growth of Ge thick layers on nominal and 6° off Si(0 0 1)\mathsemicolon Ge surface passivation by Si

International audienceWe have grown various thickness Ge layers on nominal and 6° off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of 'mounds' and a perpendicular cross-hatch were obtained on nominal surfaces. On 6° off surfaces, three sets of lines were obtained on top of the 'mounds': one along the lang1 1 0rang direction perpendicular to the misorientation direction and the other two at ~4.5° on each side of the lang1 1 0rang direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 µm thick nominal and 6° off Ge layers. Those slightly tensily strained Ge layers (R ~ 104%) were characterized by 5 × 107 cm−2 (as-grown layers) −107 cm−2 (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 °C/650 °C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An ~5 Å thick SiGe interfacial layer is self-limitedly grown at 550 °C and then thickened at 650 °C (5 Å min−1) thanks to SiH2Cl2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 Å Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 Å thick Si layer)

Negative transconductance in double-gate germanium-on-insulator field effect transistors

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Advanced GeOI structures: from material properties to high performance pMOSFETs.

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High quality Germanium On Insulator wafers with excellent hole mobility

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Tuning the electrostatic properties of silicon-on-insulating multilayer (SOIM) structures

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