A Defect-tolerant Cluster in a Mesh SRAM-based FPGA

International audienceIn this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost

RISC-V design using Free Open Source Software

International audienceThis tutorial aims to build a RISC-V processor using only free VLSI CAD tools with a symbolic technology approach (a refined Mead-Conway method as formerly used by MOSIS). The toolchain is currently organized as follow: A design description in VHDL language. Simulation with GHDL. Logical synthesis with Yosys. We use a frontend to convert VHDL into Verilog (from Alliance). Physical design (place & route) using Coriolis. DRC & LVS using Alliance. Timing analysis with Tas & Yagle. Symbolic to real translation (Alliance).Our first objective is to design a RISC-V for AMS 350nm node.The choice of symbolic technology is mainly made for three reasons: Node portability: From one symbolic layout, you may target multiple technologies. Community: Symbolic layout does not contain any NDA related information. As such it can freely be published and shared. Security.:With a published layout, everybody can check that the chip send back from the foundry is exactly what it should be (no hardware trojan)

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip

International audienceIn this paper, we present the implementation of a multi-threaded software application for pre-crash obstacle detection, using stereo vision, and the "V-disparity" algorithm, that requires intensive computation. This application runs on a generic, low cost, massively parallel, multi-processor system-on-chip (MP-SoC). This hardware architecture is suitable for automotive area with respect to performance, cost, and flexibility constraints. This hardware/software embedded application is able to process 40 stereoscopic pairs per second with 256 lines of 512 pixels images and a disparity range of 256. Our architecture is made of 8 clusters, 30 general-purpose 32-bit processors and 750 Kbytes embedded memory

MixLock: Securing Mixed-Signal Circuits via Logic Locking

International audienceIn this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a Σ∆ Analog-to-Digital Converter (ADC)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

International audienceNowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness