219 research outputs found
Coreset Clustering on Small Quantum Computers
Many quantum algorithms for machine learning require access to classical data
in superposition. However, for many natural data sets and algorithms, the
overhead required to load the data set in superposition can erase any potential
quantum speedup over classical algorithms. Recent work by Harrow introduces a
new paradigm in hybrid quantum-classical computing to address this issue,
relying on coresets to minimize the data loading overhead of quantum
algorithms. We investigate using this paradigm to perform -means clustering
on near-term quantum computers, by casting it as a QAOA optimization instance
over a small coreset. We compare the performance of this approach to classical
-means clustering both numerically and experimentally on IBM Q hardware. We
are able to find data sets where coresets work well relative to random sampling
and where QAOA could potentially outperform standard -means on a coreset.
However, finding data sets where both coresets and QAOA work well--which is
necessary for a quantum advantage over -means on the entire data
set--appears to be challenging
Efficient control pulses for continuous quantum gate families through coordinated re-optimization
We present a general method to quickly generate high-fidelity control pulses
for any continuously-parameterized set of quantum gates after calibrating a
small number of reference pulses. We find that interpolating between optimized
control pulses for different quantum operations does not immediately yield a
high-fidelity intermediate operation. To solve this problem, we propose a
method to optimize control pulses specifically to provide good interpolations.
We pick several reference operations in the gate family of interest and
optimize pulses that implement these operations, then iteratively re-optimize
the pulses to guide their shapes to be similar for operations that are closely
related. Once this set of reference pulses is calibrated, we can use a
straightforward linear interpolation method to instantly obtain high-fidelity
pulses for arbitrary gates in the continuous operation space.
We demonstrate this procedure on the three-parameter Cartan decomposition of
two-qubit gates to obtain control pulses for any arbitrary two-qubit gate (up
to single-qubit operations) with consistently high fidelity. Compared to
previous neural network approaches, the method is 7.7x more computationally
efficient to calibrate the pulse space for the set of all single-qubit gates.
Our technique generalizes to any number of gate parameters and could easily be
used with advanced pulse optimization algorithms to allow for better
translation from simulation to experiment.Comment: 9 pages, 6 figures, 2 tables; comments welcom
Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers
A massive gap exists between current quantum computing (QC) prototypes, and
the size and scale required for many proposed QC algorithms. Current QC
implementations are prone to noise and variability which affect their
reliability, and yet with less than 80 quantum bits (qubits) total, they are
too resource-constrained to implement error correction. The term Noisy
Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems
of 1000 qubits or less. Given NISQ's severe resource constraints, low
reliability, and high variability in physical characteristics such as coherence
time or error rates, it is of pressing importance to map computations onto them
in ways that use resources efficiently and maximize the likelihood of
successful runs.
This paper proposes and evaluates backend compiler approaches to map and
optimize high-level QC programs to execute with high reliability on NISQ
systems with diverse hardware characteristics. Our techniques all start from an
LLVM intermediate representation of the quantum program (such as would be
generated from high-level QC languages like Scaffold) and generate QC
executables runnable on the IBM Q public QC machine. We then use this framework
to implement and evaluate several optimal and heuristic mapping methods. These
methods vary in how they account for the availability of dynamic machine
calibration data, the relative importance of various noise parameters, the
different possible routing strategies, and the relative importance of
compile-time scalability versus runtime success. Using real-system
measurements, we show that fine grained spatial and temporal variations in
hardware parameters can be exploited to obtain an average x (and up to
x) improvement in program success rate over the industry standard IBM
Qiskit compiler.Comment: To appear in ASPLOS'1
Comparing the Overhead of Topological and Concatenated Quantum Error Correction
This work compares the overhead of quantum error correction with concatenated
and topological quantum error-correcting codes. To perform a numerical
analysis, we use the Quantum Resource Estimator Toolbox (QuRE) that we recently
developed. We use QuRE to estimate the number of qubits, quantum gates, and
amount of time needed to factor a 1024-bit number on several candidate quantum
technologies that differ in their clock speed and reliability. We make several
interesting observations. First, topological quantum error correction requires
fewer resources when physical gate error rates are high, white concatenated
codes have smaller overhead for physical gate error rates below approximately
10E-7. Consequently, we show that different error-correcting codes should be
chosen for two of the studied physical quantum technologies - ion traps and
superconducting qubits. Second, we observe that the composition of the
elementary gate types occurring in a typical logical circuit, a fault-tolerant
circuit protected by the surface code, and a fault-tolerant circuit protected
by a concatenated code all differ. This also suggests that choosing the most
appropriate error correction technique depends on the ability of the future
technology to perform specific gates efficiently
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures
Quantum computers have recently made great strides and are on a long-term
path towards useful fault-tolerant computation. A dominant overhead in
fault-tolerant quantum computation is the production of high-fidelity encoded
qubits, called magic states, which enable reliable error-corrected computation.
We present the first detailed designs of hardware functional units that
implement space-time optimized magic-state factories for surface code
error-corrected machines. Interactions among distant qubits require surface
code braids (physical pathways on chip) which must be routed. Magic-state
factories are circuits comprised of a complex set of braids that is more
difficult to route than quantum circuits considered in previous work [1]. This
paper explores the impact of scheduling techniques, such as gate reordering and
qubit renaming, and we propose two novel mapping techniques: braid repulsion
and dipole moment braid rotation. We combine these techniques with graph
partitioning and community detection algorithms, and further introduce a
stitching algorithm for mapping subgraphs onto a physical machine. Our results
show a factor of 5.64 reduction in space-time volume compared to the best-known
previous designs for magic-state factories.Comment: 13 pages, 10 figure
Resource Optimized Quantum Architectures for Surface Code Implementations of Magic-State Distillation
Quantum computers capable of solving classically intractable problems are
under construction, and intermediate-scale devices are approaching completion.
Current efforts to design large-scale devices require allocating immense
resources to error correction, with the majority dedicated to the production of
high-fidelity ancillary states known as magic-states. Leading techniques focus
on dedicating a large, contiguous region of the processor as a single
"magic-state distillation factory" responsible for meeting the magic-state
demands of applications. In this work we design and analyze a set of optimized
factory architectural layouts that divide a single factory into spatially
distributed factories located throughout the processor. We find that
distributed factory architectures minimize the space-time volume overhead
imposed by distillation. Additionally, we find that the number of distributed
components in each optimal configuration is sensitive to application
characteristics and underlying physical device error rates. More specifically,
we find that the rate at which T-gates are demanded by an application has a
significant impact on the optimal distillation architecture. We develop an
optimization procedure that discovers the optimal number of factory
distillation rounds and number of output magic states per factory, as well as
an overall system architecture that interacts with the factories. This yields
between a 10x and 20x resource reduction compared to commonly accepted single
factory designs. Performance is analyzed across representative application
classes such as quantum simulation and quantum chemistry.Comment: 16 pages, 14 figure
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