Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics

Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm2/V·s and their on/off ratio was in the range of 104–105. The threshold voltages of the programmed and erased states were negligibly changed up to 103 cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics

Characterization of a Photodiode Coupled with a Si Nanowire-FET on a Plastic Substrate

In this study, a laterally coupled device composed of a photodiode and a Si nanowires-field-effect transistor (NWs-FET) is constructed on a plastic substrate and the coupled device is characterized. The photodiode is made of p-type Si NWs and an n-type ZnO film. The Si NWs-FET is connected electrically to the photodiode in order to enhance the latter’s photocurrent efficiency by adjusting the gate voltage of the FET. When the FET is switched on by biasing a gate voltage of −9 V, the photocurrent efficiency of the photodiode is three times higher than that when the FET is switched off by biasing a gate voltage of 0 V

Updates on the genetic variations of Norovirus in sporadic gastroenteritis in Chungnam Korea, 2009-2010

Previously, we explored the epidemic pattern and molecular characterization of noroviruses (NoVs) isolated in Chungnam, Korea in 2008, and the present study extended these observations to 2009 and 2010. In Korea, NoVs showed the seasonal prevalence from late fall to spring, and widely detected in preschool children and peoples over 60 years of age. Epidemiological pattern of NoV was similar in 2008 and in 2010, but pattern in 2009 was affected by pandemic influenza A/H1N1 2009 virus. NoV-positive samples were subjected to sequence determination of the capsid gene region, which resolved the isolated NoVs into five GI (2, 6, 7, 9 and 10) and eleven GII genotypes (1, 2, 3, 4, 6, 7, 8, 12, 13, 16 and 17). The most prevalent genotype was GII.4 and occupied 130 out of 211 NoV isolates (61.6%). Comparison of NoV GII.4 of prevalent genotype in these periods with reference strains of the same genotype was conducted to genetic analysis by a phylogenetic tree. The NoV GII.4 strains were segregated into seven distinct genetic groups, which are supported by high bootstrap values and previously reported clusters. All Korean NoV GII.4 strains belonged to either VI cluster or VII cluster. The divergence of nucleotide sequences within VI and VII intra-clusters was > 3.9% and > 3.5%, respectively. The "Chungnam(06-117)/2010" strain which was isolated in June 2010 was a variant that did not belong to cluster VI or VII and showed 5.8-8.2%, 6.2-8.1% nucleotide divergence with cluster VI and VII, respectively

Enhanced Thermoelectric Characteristics of Ag2Se Nanoparticle Thin Films by Embedding Silicon Nanowires

A solution-processable Ag2Se nanoparticle thin film (NPTF) is a prospective thermoelectric material for plastic-based thermoelectric generators, but its low electrical conductivity hinders the fabrication of high performance plastic-based thermoelectric generators. In this study, we design Ag2Se NPTFs embedded with silicon nanowires (SiNWs) to improve their thermoelectric characteristics. The Seebeck coefficients are −233 and −240 µV/K, respectively, for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs. For the Ag2Se NPTF embedded with SiNWs, the electrical conductivity is improved from 0.15 to 18.5 S/m with the embedment of SiNWs. The thermal conductivities are determined by a lateral thermal conductivity measurement for nanomaterials and the thermal conductivities are 0.62 and 0.84 W/(m·K) for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs, respectively. Due to the significant increase in the electrical conductivity and the insignificant increase in its thermal conductivity, the output power of the Ag2Se NPTF embedded with SiNWs is 120 times greater than that of the Ag2Se NPTF alone. Our results demonstrate that the Ag2Se NPTF embedded with SiNWs is a prospective thermoelectric material for high performance plastic-based thermoelectric generators

Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

In this study, we examine the effect of interface trap states on the electrical characteristics of single-gated feedback field-effect transistors (FBFETs) using a commercially available computer-aided design simulation package. Interface trap states exist between the channels and the oxide layers, and these trap states act as acceptor-like trap states in regions of higher energy than the intrinsic Fermi energy ( $E_{\mathrm {i}}$ ) and as donor-like trap states in regions of lower energy than $E_{\mathrm {i}}$ in the energy band. The density distribution peaks at $E_{\mathrm {i}}$ + 0.28 eV for the acceptor-like trap states and at $E_{\mathrm {i}}$ – 0.28 eV for the donor-like trap states. The occupation mechanism of these trap states is analyzed by the density of the interface states and trapped charges, the energy band diagram, and the current-voltage curves. In n-channel (p-channel) FBFETs, the latch-up voltage varies by approximately 0.01 V as the acceptor-like (donor-like) trap states increase, whereas the effect of the donor-like (acceptor-like) trap states is negligible. Moreover, the FBFETs exhibit an operating speed of 4 ns and retention time of 900 s during a memory operation, despite the existence of the interface states

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption

Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics

<p>Abstract</p> <p>Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm²/V&#183;s and their on/off ratio was in the range of 10⁴&#8211;10⁵. The threshold voltages of the programmed and erased states were negligibly changed up to 10³ cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics.</p

Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors

Abstract In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 1012 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption