Enhanced write performance of a 64-Mb phase-change random access memory

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-mu m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively

A 0.18-mu m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge2Sb2Te5) into 0.18-mum CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30degreesC

A 0.1-mu m 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal x 2 write and can be increased to similar to 2.67 MB/s with x 16 write. Endurance and retention characteristics are measured to be 10(7) cycles and ten years at 99 degrees C