The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with intrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth, wide dynamic range and simple operation. Containing 4 channels of 256 samples per channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOS process and uses a high-performance package that is 8 mm on a side. It has a 1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses ~128 mW while operating at 2 G-samples/s and full trigger rates. With a standard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator running at half the sample rate (e.g., a 1 GHz oscillator yields 2 G-samples/s). Because of its purely-digital synchronous nature, the SST has ps-level timing uniformity that is independent of sample frequencies spanning over 6 orders of magnitude: from under 2 kHz to over 2 GHz. Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. When operating as common-stop device, the time of the stop, modulo 256 relative to the start, is read out along with the sampled signal values. Each of the four channels integrates dual-threshold trigger circuitry with windowed coincidence features. Channels can discriminate signals with ~1mV RMS resolution at >600 MHz bandwidth.Comment: 3 pages, 6 figures, 1 table, submitted for publication in the Conference Record of the 2014 IEEE Nuclear Science Symposium, Seattle, WA, November 201

The SST Multi-G-Sample/s Switched Capacitor Array Waveform Recorder with Flexible Trigger and Picosecond-Level Timing Accuracy

The design and performance of a multi-G-sample/s fully-synchronous analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. Containing 4 channels of 256 samples per channel and fabricated in a 0.25 {\mu}m CMOS process, it has a 1.9V input range on a 2.5V supply, achieves 12 bits of dynamic range, and uses ~160 mW while operating at 2 G-samples/s and full trigger speeds. With a standard 50 Ohm input source, the SST's analog input bandwidth is ~1.3 GHz within about +/-0.5 dB and reaches a -3 dB bandwidth of 1.5 GHz. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator, interleaved to double its speed (e.g., a 1 GHz clock yields 2 G-samples/s). It can operate over 6 orders of magnitude in sample rates (2 kHz to 2 GHz). Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. Each of the four channels integrates dual-threshold discrimination of signals with ~1 mV RMS resolution at >600 MHz bandwidth. Comparator results are directly available for simple threshold monitoring and rate control. The High and Low discrimination can also be AND'd over an adjustable window of time in order to exclusively trigger on bipolar impulsive signals. Trigger outputs can be CMOS or low-voltage differential signals, e.g. 1.2V CMOS or positive-ECL (0-0.8V) for low noise. After calibration, the imprecision of timing differences between channels falls in a range of 1.12-2.37 ps sigma at 2 G-samples/s.Comment: 9 pages, 16 figures, 1 tabl

Multi-Gigahertz Synchronous Sampling and Triggering (SST) Circuit with Picosecond Timing Resolution

The Antarctic Ross Ice shelf ANtenna Neutrino Array (ARIANNA) particle physics experiment aims to detect ultra-high energy neutrinos originating outside our solar system. A second generation detector prototype for the experiment has been developed and successfully deployed in Antarctica. The second generation detector is based on the Synchronous Sampling and Triggering (SST) integrated circuit. This dissertation focuses on the design and performance of the SST chip.Fabricated in a 0.25um CMOS process, the SST is a low power data acquisition circuit that monitors for potential neutrino signals and preserves candidate signals. The waveform capture is performed with a 256-cell time-interleaved sampling array. Continuous sampling operation is achieved through circular cycling across the array. The synchronous sampling clock generation allows for sampling rates that span six orders of magnitude (i.e. ranging between 2.0 KHz and 2.0 GHz). The analog bandwidth (-3dB frequency) of the SST reaches 1.5 GHz, allowing for the capture of frequency components up to the Nyquist frequency. The SST integrates four channels of waveform capture functionality into a single chip. Each SST channel includes event triggering to initiate the signal capture of neutrino events, and to reject random noise signals. Events are triggered based on outputs from a pair of high speed comparators that monitor for bipolar threshold crossings. Multiple triggering options are available on the SST, including direct output of the comparator signals and triggering on dual threshold crossings occurring within a programmable time window. The SST chip utilizes an external low jitter LVDS oscillator to synchronously generate an internal sampling clock with low timing jitter. The fixed pattern timing noise was characterized through two different approaches: a stochastic zero crossing method and a Monte Carlo based simulated annealing method. After calibrating for fixed pattern timing noise, the SST achieves inter channel timing resolutions between 1.15 ps (RMS) and 2.36 ps (RMS)