On-Wafer Microwave De-Embedding Techniques

Wireless communication technology has kept evolving into higher frequency regime to take advantage of wider data bandwidth and higher speed performance. Successful RF circuit design requires accurate characterization of on-chip devices. This greatly relies on robust de-embedding technique to completely remove surrounding parasitics of pad and interconnects that connect device to measurement probes. Complex interaction of fixture parasitic at high frequency has imposed extreme challenges to de-embedding particularly for lossy complementary metal oxide semiconductor (CMOS) device. A generalized network de-embedding technique that avoids any inaccurate lumped and transmission line assumptions on the pad and interconnects of the test structure is presented. The de-embedding strategy has been validated by producing negligible de-embedding error (<−50 dB) on the insertion loss of the zero-length THRU device. It demonstrates better accuracy than existing de-embedding techniques that are based on lumped pad assumption. For transistor characterization, the de-embedding reference plane could be further shifted to the metal fingers with additional Finger OPEN-SHORT structures. The resulted de-embedded RF parameters of CMOS transistor show good scalability across geometries and negligible frequency dependency of less than 3% for up to 100 GHz. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization

Flicker noise fluctuations in deep submicron MOSFETs

166 p.This thesis investigates the effects of technology scaling on the flicker (or \lf) noise performance of deep submicron complementary metal-oxide-semiconductor (CMOS) transistors. Two major effects have been investigated, namely the employment of different gate dielectric growth and subsequent nitridation conditions, and the effects of geometry scaling. The first part of this work focus on the study of these two effects within the 0.25p.m technology node. Subsequently the scope of this study has been widened to examine the effects of scaling across a spectrum of technology nodes, namely 0.35um, 0.25um, 0.18pm and 0.13um. Finally the scope is further extended to cover the offering of different process flavours, as well as geometry scaling for the 0.13pm technology node.DOCTOR OF PHILOSOPHY (EEE

Analytical and experimental characterization of sub-half micron MOS devices

We present in this thesis the characterization of deep submicrometer (the device channel length ranges from 0.25um to l.Oum) lightly-doped drain (LDD) pMOSFETs operating in a Bi-MOS structure. The Bi-MOS structure is essentially a device operating with its source-body junction forward biased. Consequently, there is an additional current component, the lateral bipolar current, flowing beneath the principal MOS current.Master of Engineerin

A temperature-dependent DC model for quarter-micron LDD pMOSFET’s operating in a Bi-MOS structure

A temperature-dependent analytical model for deep submicrometer LDD p-channel devices operating in a Bi-MOS structure is reported for the first time. This model is based on experimental data obtained from 0.25-µm process wafers with a wide range of technologies (0.25–1.0µm). The measurements have been performed within the temperature range 223–398 K (50C to +125C). The model accounts for the effects of independently biasing the source, drain, gate and body potentials, scaling, and the influence of temperature on the threshold voltage and the device currents. The effect of temperature on the device transconductance and the output conductance have also been examined. The results revealed that close agreement between the analytical model and the experimental has been achieved. Comparisons between the principal MOS current and the lateral bipolar current have been made to demonstrate the improvement of the latter with temperature for the quarter-micron devices.Published versio

Method to fabricate horizontal air columns underneath metal inductor

US7105420Granted Paten

Method to fabricate horizontal air columns underneath metal inductor

US7573081Granted Paten

Method of making spiral-type RF inductors having a high quality factor (Q)

US6140197Granted Paten

High frequency drain current noise modeling in MOSFETs under sub-threshold condition

A new high frequency drain current noise model was developed for MOSFETs under sub-threshold condition. A simple parameter extraction technique is proposed, which utilizes Y-parameter analysis on the RF small-signal equivalent circuit. Good agreement has been obtained between the predicted and measured results up to 20 GHz.Published versio

A new unified model for channel thermal noise of deep sub-micron RFCMOS

A new unified model for circuit simulation is presented to predict the high frequency channel thermal noise of deep sub-micron MOSFETs in strong inversion region. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities of the devices fabricated in a 0.13μm RFCMOS technology process are compared to the channel noise directly extracted from RF noise measurements.Published versio

Analytical high frequency channel thermal noise modeling in deep sub-micron MOSFETs

A simple high frequency channel thermal noise model was developed for MOSFETs in strong inversion region. Short channel effects such as channel length modulation effect and mobility degradation due to vertical field were taken into account in the current-voltage model and channel thermal noise model. It was found that the long channel Tsividis’ noise model is still valid for short channel devices by including the proposed effective mobility model and the channel length modulation effect. Good agreement has been obtained between the simulated and measured results across different frequencies, gate biases and drain biases.Published versio