Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars

The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity

PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique

This paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system

Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators

The direct frequency modulation of a phase locked loop suffers from limited modulation bandwidth. To overcome this limitation, the modulation signal can be pre-emphasized by means of a high-pass filter. Unfortunately, the incorrect equalization of the PLL transfer function causes modulation error. This paper introduces a new method to adaptively match the transfer functions of the PLL and the pre-emphasis filter over environmental and process variations. The technique is verified using a time-domain model of a digital PLL designed for the generation of chirp signals for FMCW radar sensors. The new adaptive digital pre-emphasis technique enables the generation of highly-linear fast chirps with significant reduction of the idle time

Digital frequency synthesizer with robust injection locked divider

The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range

Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with respect to the more conventional triangular waveform. Such a signal, however, features a very large bandwidth that requires the adoption of a two-point injection scheme. This paper, after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the accuracy of frequency modulation, presents a novel automatic pre-distortion engine, operating fully in background, which linearizes the tuning characteristic. The 19.7-mA fractional-N PLL having an rms jitter of 213 fs and an in-band fractional spur of -58 dBc is capable of synthesizing fast chirps with 173-MHz/μs maximum slope and an idle time of less than 200 ns after an abrupt frequency step with no over or undershoot

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation

Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is -150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 μs, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL

A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur

This paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB