Efficient time-to-digital converters in 20 nm FPGAs with wave union methods

The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, a famous earlier study concluded that the WU method is not suitable for UltraScale field-programmable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new sub-tapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDC combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs

Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA

128-channel high-linearity resolution- adjustable time-to-digital converters for LiDAR applications : software predictions and hardware implementations

This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in a good agreement and show that the proposed design has great potential for multichannel applications; the averaged DNL_(pk-pk) and INL_(pk-pk) are close to or even less than 0.05 LSB in multichannel designs

Low hardware consumption, resolution-configurable gray code oscillator time-to- digital converters implemented in 16nm, 20nm and 28nm FPGAs

This paper presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (GCO-TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes LUTs as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution. 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration. 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively

Multichannel time-to-digital converters with automatic calibration in Xilinx Zynq-7000 FPGA devices

This paper proposes a weighted histogram method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) 16 in low-cost advanced RISC machine (ARM)-based field-programmable gate arrays (FPGAs). The proposed method significantly reduces nonlinearity induced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 32-channel TDC system in a low-cost Zynq-7000 ARM-based FPGA, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps (LSB = 9.83 ps) with good uniformity, achieving an averaged peak-peak differential nonlinearity (DNLpk-pk) of 0.27 LSB, and an averaged peak-to-peak integral nonlinearity 28 (INLpk-pk) of 0.67LSB

Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications

This paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). This method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. Therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. The proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon

Assessing Novel Lidar Modalities for Maximizing Coverage of a Spaceborne System through the Use of Diode Lasers

Current satellite lidars have sparse spatial coverage, leading to uncertainty from sampling. This complicates robust change detection and does not allow applications that require continuous coverage. One potential way to increase lidar sampling density is to use more efficient lasers. All current spaceborne lidars use solid-state lasers with a limited efficiency of 5–8%. In this paper, we investigate the potential for using diode lasers, with their higher efficiencies, as an alternative. Diode lasers have reported efficiencies of about 25% and are much smaller and lighter than solid-state lasers. However, they can only emit good beam quality at lower peak powers, which has so far prevented them from being used in spaceborne lidar applications. In this paper, we assess whether the novel lidar modalities necessitated by these lower peak powers are suitable for satellite lidar, determined by whether they can match the design performance of GEDI by being able to accurately measure ground elevation through 98% canopy cover, referred to as having “98% beam sensitivity”. Through this, we show that a diode laser can be operated in pulse train or pulse compressed lidar (PCL) mode from space, using a photon-counting detector. In the best case scenario, this setup requires a detected energy of Edet=0.027 fJ to achieve a beam sensitivity of 98%, which is less than the 0.28 fJ required by a full-waveform solid-state lidar instrument, exemplified by GEDI. When also accounting for the higher laser and detector efficiency, the diode laser in pulse train mode requires similar shot energy as a photon counting solid-state laser such as ICESat-2 which along with the higher laser efficiency could result in a doubling of coverage. We conclude that there is a clear opportunity for diode lasers to be used in spaceborne lidars, potentially allowing wider coverage through their higher efficiencies

A two-stage interpolation time-to-digital converter implemented in 20 nm and 28 nm FGPAs

This article presents a two-stage interpolation time- to-digital converter (TDC), combining a Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL- TDC). The proposed TDC uses the Nutt method to achieve a broad, high-resolution measurement range. It utilizes look-up tables (LUTs)-based gray code oscillators (GCOs) to build a VGCO-TDC as the first-stage interpolation for fine-time measurements. Then the overtaking residual from the VGCO-TDC is measured by a TDL-TDC to achieve the second-stage interpolation. Due to the two-stage interpolation architecture, the carry-chain-based delay line only needs to cover the resolution of the VGCO-TDC. Hence, we can reduce the delay-line length and related hardware resource utilization. We implemented and evaluated a 16-channel TDC system in Xilinx 20-nm Kintex-UltraScale and 28-nm Virtex-7 field-programmable gate arrays (FPGAs). The Kintex-UltraScale version achieves an average resolution (least significant bit, LSB) of 4.57 picoseconds (ps) with 4.36 LSB average peak-to-peak differential nonlinearity (DNLpk-pk). The Virtex-7 version achieves an average resolution of 10.05 ps with 2.85 LSB average DNLpk-p

A 192×128 Time Correlated SPAD Image Sensor in 40-nm CMOS Technology

A 192 X 128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCSPC) image sensor is implemented in STMicroelectronics 40-nm CMOS technology. The 13% fill factor, 18.4\,\,\mu \text {m} \times 9.2\,\,\mu \text{m} pixel contains a 33-ps resolution, 135-ns full scale, 12-bit time-to-digital converter (TDC) with 0.9-LSB differential and 5.64-LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219-ps full-width half-maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kframes/s through 64 parallelized serial outputs. Cylindrical microlenses with a concentration factor of 3.25 increase the fill factor to 42%. The median dark count rate (DCR) is 25 Hz at 1.5-V excess bias. A digital calibration scheme integrated into a column of the imager allows off-chip digital process, voltage, and temperature (PVT) compensation of every frame on the fly. Fluorescence lifetime imaging microscopy (FLIM) results are presented

Hyperspectral imaging under low illumination with a single photon camera

Conventional sensors for hyperspectral imaging are limited by noise when operated in low illumination conditions. Recent advances in single-photon avalanche diode (SPAD) arrays provide image sensors capable of single photon counting imaging. Such devices provides camera systems which can operate under low illumination levels and high frame rates, with fully digital in-pixel processing capabilities. Here, we present a hyperspectral imaging system based on low level illumination of a target scene using nine LEDs, each with different emission wavelengths. The backscattered light is captured by a SPAD camera, which can recover spectral information based on the number of photon counts received for each illumination wavelength