UPPER THORACIC SPINE (D2-D3) FRACTURE-DISLOCATION WITHOUT SPINAL CORD INJURY: A CASE REPORT

Fracture dislocations of the thoracic spine in extremly rare and when it occurs,it is considered the most unstable of spinal injuries and is almost always associated with injury to the spinal cord due to narrow spinal canal dimensions.Very few neurologically intact cases of thoracic spine fracture dislocation have been reported in the literature ,which are mostly around the dorsolumbar junction and none in the upper thoracic spine.Here we report a case of 44 years old man who was in a road traffic accident and diagnosed with fracture dislocation of D2 over D3 vertebra with no neurological deficit.Patient was treated with Posterior spinal stabilization,reduction and D2 laminectomy.Patient remanined neurologically intact post operatively.Here we discuss the significance of this injury and the neural sparing mechanism of posterior neural arch disruption(bilateral pedicle fracture and lamina fracture),which  preserves the spinal canal and the spinal cord from being damaged.We also discuss about the usefulness of CT scan and MR imaging in these injuries and the surgical approaches used in treating them.     Keywords-fracture dislocation,thoracic spine,surgical approaches Â&nbsp

A predictor-based power-saving policy for DRAM memories

Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%

Improved Power Modeling of DDR SDRAMs

Abstract — Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power consumption, but lack accurate and generic power models. The most popular SDRAM power model provided by Micron, is found to be inaccurate or insufficient for several reasons. First, it does not consider the power consumed when transitioning to power-down and self-refresh modes. Second, it employs the minimal timing constraints between commands from the SDRAM datasheets and not the actual duration between the commands as issued by an SDRAM memory controller. Finally, without adaptations, it can only be applied to a memory controller that employs a close-page policy and accesses a single SDRAM bank at a time. These critical issues with Micron’s power model impact the accuracy and the validity of the power values reported by it and resolving them, forms the focus of our work. In this paper, we propose an improved SDRAM power model that estimates power consumption during the state transitions to power-saving states, employs an SDRAM command trace to get the actual timings between the commands issued and is generic and applicable to all DDRx SDRAMs and all memory controller policies and all degrees of bank interleaving. We quantitatively compare the proposed model against the unmodified Micron model on power and energy for DDR3-800. We show differences of up to 60 % in energy-savings for the precharge power-down mode for a power-down duration of 14 cycles and up to 80 % for the self-refresh mode for a self-refresh duration of 560 cycles

Memory controllers for mixed-time-criticality systems: architectures, methodologies and trade-offs

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template

Architectures, Methodologies and Trade-offs

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.info:eu-repo/semantics/publishedVersio

Power/performance trade-offs in real-time SDRAM command scheduling

Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations

Dynamiczna analiza mechaniczna i analiza termiczna kompozytów z niepoddanymi obróbce włóknami Coccinia indica

A natural fiber reinforced polymer matrix composites (FRCs) was prepared by the compression molding method. The natural fiber named Coccinia indica (CI) was employed to fabricate FRCs. The impact of fiber length on storage modulus, loss modulus and loss of weight in the FRCs were determined using dynamic mechanical analysis (DMA) and thermogravimetric analysis (TGA). The results revealed that a fiber length of 40 mm shows better storage modulus and nominal loss modulus owing to the higher interfacial bonding between fiber and matrix. In other investigated fiber lengths, the storage modulus is poor and loss modulus is high, which is due to inefficient stress transfer.Metodą wytłaczania przygotowano próbki kompozytów (FRC) na osnowie polimerowej wzmocnionej włóknami naturalnymi Coccinia indica (CI). Wpływ długości zastosowanych włókien na moduł zachowawczy, moduł stratności i ubytek masy badanych FRC oceniano za pomocą dynamicznej analizy mechanicznej (DMA) i analizy termograwimetrycznej (TGA). Stwierdzono, że kompozyty z udziałem włókien o długości 40 mm wykazują korzystniejszy moduł zachowawczy i nominalny moduł stratności, dzięki lepszemu wiązaniu międzyfazowemu włókna z osnową. W wypadku kompozytów z zawartością włókien o innych długościach moduł zachowawczy jest mały, a moduł stratności duży, co wynika z nieefektywnego przenoszenia naprężeń

Towards variation-aware system-level power estimation of DRAMs : an empirical approach

DRAM vendors provide pessimistic current measures in memory datasheets to account for worst-case impact of process variations and to improve their production yield, leading to unrealistic power consumption estimates. In this paper, we first demonstrate the possible effects of process variations on DRAM performance and power consumption by performing Monte-Carlo simulations on a detailed DRAM cross-section. We then propose a methodology to empirically determine the actual impact for any given DRAM memory by assessing its performance characteristics during the DRAM calibration phase at system boot-time, thereby enabling its optimal use at run-time. We further employ our analysis on Micron's 2Gb DDR3-1600-x16 memory and show considerable over-estimation in the datasheet measures and the energy estimates (up to 28%), by using realistic current measures for a set of MediaBench applications