Catching Up with the Joneses: Heterogeneous Preferences and the Dynamics of Asset Prices

We analyze a general equilibrium exchange economy with a continuum of agents who have 'catching up with the Joneses' preferences and differ only with respect to the curvature of their utility functions. While individual risk aversion does not change over time, dynamic redistribution of wealth among the agents leads to countercyclical time variation in the Sharpe ratio of stock returns. We show that both the conditional risk premium and the return volatility are negatively related to the level of stock prices, as observed empirically. Therefore, our model exhibits many of the empirically observed properties of aggregate stock returns, e.g., patterns of autocorrelation in returns, the 'leverage effect' in return volatility and long-horizon return predictability. For comparison, otherwise similar representative agent economies with the same type of preferences exhibit counter-factual behavior, e.g., a constant Sharpe ratio of returns and procyclical risk premium and return volatility.

Influence of electron scatterings on thermoelectric effect

In this work, we employed non-equilibrium Green's function to investigate the electron transport properties in the nanowire with the presence of scatterings. The scattering mechanism is modelled by using the concept of B\"uttiker probe. The effect of electron scattering is analyzed under three conditions: absence of external field; with a bias voltage; and with a finite temperature difference. It is found weak and strong scatterings strength affect the electron transport in different ways. In the case of weak scattering strength, electron trapping increase the electron density, hereafter boost the conductance significantly. Although the increment in conductance would reduce the Seebeck coefficient slightly, the power factor still increases. In the case of strong scattering strength, electron diffraction causes the redistribution of electrons, accumulation of electron at the ends of the wire blocks current flow; hence the conductance is reduced significantly. Although the Seebeck coefficient increases slightly, the power factor still decreases. The power factor is enhanced by 6%-18%, at the optimum scattering strength

Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformation

This paper proposes new structures for realizing tunable 2-D fan and elliptical filters with different spectral characteristics using McClellan transformation. The 1-D prototype is a variable digital filter obtained from the interpolation of a set of desirable impulse responses and is implemented using the Farrow structure. The coefficients of the sub-filters and the transformation parameters in the Farrow structure are represented in SOPOT, which can be easily implemented as simple shift-and-add operations. Furthermore, the transformation part can be shared between the sub-filters leading to significant saving in hardware complexity. Several design examples are given to demonstrate the effectiveness and feasibility of the proposed approach.published_or_final_versio

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio